Mike Engbretson, USB Test Solution Marketing Manager, Tektronix, spoke with T&MW
Senior Technical Editor Martin Rowe about the technology and testing of USB 3.0
transmitters and receivers.
It seems as though USB 3.0 is borrowing heavily from PCI Express Gen2. I'd like to cite some
similarities and differences. For one thing, PCIeGen2 uses multiple lanes, but USB does not.
The signaling is at the rate of PCI-E 2.0, but the transmission channel is very similar to SATA
(Serial ATA). The signaling challenges in USB 3.0 will be high as the target ‘worst case channel’
for USB 3.0 is 12” of FR4 motherboard, two connectors, and 3 meters of cable. This aggressive
specification will present many new test challenges for designers. Here is some background
reading on similarities:
How it’s like PCI Express:
From the diagram at the end of this document, the signaling interface is a bi-directional full duplex
bus. 8B/10B Encoded NRZ (non-return to zero) data is transmitted from the Host to the Device
and vice versa at full data rate. The signaling is ~1V differential CMOS with a CM (common
mode) bias of 500 mV at the Transmitter. AC coupling is specified at the transmitter. In PCI
Express, the connector is the interface between host and device. Host and Device Channels are
typically very short (about 1–2” in length).
How it’s like SATA:
Since USB 3.0 is a cable interconnect, the changes to the specification need to be considered. In
PCI Express the RefClk (100 MHz Reference Clock) is distributed from the host to the device, so
SSC of 0.5% of the signaling rate shares the same profile. As in SATA, the host and device have
their own local RefClks, so the PLL clock recovery needs to be designed to account for
differences in RefClk A and RefClk B profiles. Also, like SATA, there’s a cabled interface for USB
3.0.
Q: Will it be better to use a lower-bandwidth scope at the receiver to minimize the added jitter
from the instrument in the measurements?
A: With today’s higher bandwidth scopes, an engineer can control the added noise/jitter by
moving the bandwidth control on the instrument to the proper level while ensuring solid signal
integrity through an oversampling of the acquired signal(s) on all channels of the oscilloscope.
Therefore, if the customer will be making USB 3.0 measurements on both transmitter and
receiver, it is advisable to have a single instrument with 12.5 GHz capability, leveraging the
higher bandwidth capability at 5th harmonic on the transmitter where the signal’s transition time is
as fast as it would be on a PCI Express Gen 2 (5 Gb/sec) signal. Then, using the same
instrument, change the bandwidth to a lower level; therefore controlling the jitter/noise profile and
making accurate receiver measurements.
Another point to consider is emulation of a physical channel (like SATA) for early development
needs. The same oscilloscope should come with filter capability that enables the inclusion of a
unique filter setup to emulate the channel.
Q: The rise time and jitter will be important. What rise time can we expect to measure?
A: Very similar to PCI Express Gen 2, so the rise time at the transmitter will be ~35-40
picoseconds. See PPT slide for reference.
Q: How much jitter will be acceptable when measured at the transmitter? Are measurements at
the transmitter chip or at the USB connector?
A: Because of the channel complexities, the specification will put the responsibility on the chipset
vendor(s) to provide reference designs that meet very strict signaling requirements at the
Connector, or ‘Compliance Measurement Plane.’ Maximum allowable jitter levels are being
determined for inclusion in the spec, but they will be minimal due to the high speed of the data
signal.
Q: He also mentioned that engineers will need a 12.5 GHz oscilloscope. Will that be required by
the standard as it is with PCIe?
A: For early customer design (primarily silicon development) customers have opted for 12.5GHz
scopes and above, due to the ‘5th harmonic’ rule of thumb, providing them with a better indication
of transition times for their transmitter’s output. It is yet uncertain what bandwidth requirements
will be for USB 3.0 test standards, but it is advisable to provide 5th harmonic visibility on
transmitter characterization, consistent with PCI Express Gen 2 testing guidance.
Q: Will 12.5 GHz be needed at the transmitter and receiver or just the transmitter?
A: It is likely that customers doing measurements for USB 3.0 compliance will settle on a range of
8 GHz to 12.5GHz oscilloscopes depending on where they are making their measurements.
Using a 12.5-GHz oscilloscope for transmitter dependant measurements will likely be the norm
due to the 5th harmonic implications for the 5 Gb/sec data rate and comparisons to PCI Express
Gen 2 design work.
There are advantages to using a single instrument to do all (Tx/Rx/Channel) early verification
work. Therefore, a 12.5 GHz oscilloscope is recommended in that case.
Q: Signal integrity will become an issue. When testing a USB 3.0 receiver, will the eye be opened
or closed and thus require equalization?
A: The eye will be closed, and EQ (equalization) will be applied through a CTLE (continuous time
linear equalization) function that is being written into the USB 3.0 specification. This will allow for
an open eye at the receiver.
Q: Does that mean USB 3.0 receivers will need stress testing with closed eyes?
A: Yes, it will be the first broadly deployed PC industry specification that has receiver testing as a
normative requirement.
Q: What kind of stresses in terms of jitter, intersymbol interference, etc. will need to be placed on
a test signal?
A: The compliance requirement is to apply the stressed eye (with random and periodic jitter
components) through a physical channel. The physical channel will provide the ISI. In the cases
where no physical channel is available (early silicon development takes place without a channel
in most instances) there are signal sources which provide the ability to emulate the physical
channel by including ISI. This allows those silicon vendors to test their receivers before a physical
channel is available.
Gigabit Data Rates Require High-Bandwidth Test
Fundamental
Frequency
Serial Bus Data Rate
3rd
Harmonic
5th
Harmonic
2.5 Gb/s (PCI-Express)
1.25 GHz
3.75 GHz
6.25 GHz
3.0 Gbps (SATA II)
1.5GHz
4.5 GHz
7.5 GHz
3.125 Gbps (XAUI)
1.56 GHz
4.69 GHz
7.81 GHz
4.25 Gb/s (Fibre Channel)
2.125 GHz
6.375 GHz
10.625 GHz
4.8 Gb/s (FBD)
2.4 GHz
7.2 GHz
12.0 GHz
5.0 Gb/s (PCI-Express 2.0/USB3.0)
2.5 GHz
7.5 GHz
12.5 GHz
6.0 Gb/s (SATA III)
3.0 GHz
9.0 GHz
15.0 GHz
6.25 Gb/s (2x XAUI) (CEI)
3.125 GHz
9.375 GHz
15.625 GHz
6.4Gb/s (Front Side Bus)
3.2 GHz
9.6 GHz
16.0 GHz
8.0 Gb/s (Front Side Bus)
4.0 GHz
12.0 GHz
20.0 GHz
8.0 Gb/s (PCI-Express 3.0)
4.8 GHz
14.4 GHz
24.0 GHz
Serdes Sample Point
3rd
Harmonic
Captured
5th
Harmonic
Captured
 GHz bandwidth performance
ensures signal fidelity
 Provides critical accuracy for
characterization and analysis
 Ensures complete testing of
design
margins
13 GHz Scope
DUT Signal
Measurement System Bandwidth Required
Rise/Fall time
(20%-80%)
10% Accuracy
5% Accuracy
3% Accuracy
50 ps
8.0 GHz
9.6 GHz
11.2 GHz
40 ps
10.0 GHz
12.0 GHz
14.0 GHz
30 ps
13.3 GHz
16.0 GHz
18.7 GHz
20 ps
20 GHz
24 GHz
28 GHz