EE 414/514
VHDL DESIGN
Dr. J.A. Starzyk
FINAL
Tuesday, November 22, 2005
THIS IS A CLOSED BOOK EXAM
Name:
Box #:
Note:
1)
2)
Problem
All scratch and problem papers must be turned in.
Estimated times required to complete problems are indicated.
1
Weight
(points)
15
Estimated Time
(minutes)
10
2
20
20
3
20
20
4
10
10
5
20
20
6
15
20
100
100
TOTAL
Examiner' Use
only
.
.
GOOD LUCK!!!
1
Problem 1:
Check true or false next to each statement:
2
Problem 2:
Complete the test bench for the 3-bit parity detector circuit. The input and output for this
circuit are:
Entity Parity_det is
Port (
Input : in bit_vector (2 downto 0);
Output: out bit
);
end Parity_det;
This circuit provide output = ‘0’ when the number of ‘1’s in the input vector is even,
otherwise output =’1’.
The test vectors are provided as follows:
“0000”
“0011”
“0101”
“0110”
“1001”
“1010”
“1100”
“1111”
In each vector, the included elements are: “Input(2:0) & Output”. The test vectors are
stored in a text file “test.in”. Please write a test bench for this circuit using the text file.
(Hints:
Include the component “Parity_det” in your architecture
Use “assert” statement to report that there are errors. )
3
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
entity TB_Parity is
end TB_Parity;
architecture BEH of TB_Parity is
begin
READ_vector : process
file INFILE: text is in "test.in";
variable LINE_BUFFER : line;
variable VECTOR : std_logic_vector(3 downto 0);
begin
while (not endfile(INFILE)) loop
readline (INFILE, LINE_BUFFER);
read (LINE_BUFFER, VECTOR) ;
wait;
end process;
End architecture BEH;
4
Problem 3:
1). Assume you need to design a circuit that takes input as a serial bit stream and outputs
a “1” whenever the sequence “111” occurs. Overlaps must be considered. For instance,
if “……..0111110…” happens, then the output should remain active for three consecutive
clock cycles.
A FSM that implements this circuit has the state diagram as shown in Fig. 1. There are
four states, which called ZERO, ONE, TWO and THREE, which correspond to the
number of consecutive “1”s detected.
Fig. 1 FSM diagram
(1) Write a VHDL model for this finite state machine. The input and output signals are
d: input bit stream
clk: clock signal
rst: the asynchronous reset signal, forcing the state go back to state “ZERO”.
q: output signal
Assume all the transitions happen during rising edge of the “clock”.
Note: write your code in the next page.
(2) Assume that the input signal stream is “0111101100”, what is your output signal if the
FSM was initially at ZERO state?
(3). What type of this FSM it is?
5
Library IEEE;
Use IEEE. Std_logic_1164.all;
Entity string_detector is
Port (
);
End string_detector;
architecture FSM of string_detector is
end FSM;
6
Problem 4:
Read the following VHDL code to determine what type of hardware storage element it
infers.
Entity storage_element is
Port (
d, clock, reset: IN bit;
q, q_bar:
OUT bit
);
End storage_element;
architecture RTL of storage_element is
signal temp: bit;
begin
process (clock, d, reset, temp)
begin
if reset = '1' then
temp <= '0';
elsif clock'event and clock = '1' then
temp <= d;
end if;
end process;
q <= temp;
end RTL;
(a)
(b)
(c)
(d)
(e)
Latch with asynchronous reset
Latch with synchronous reset
Flip flop with synchronous reset
Flip flop with asynchronous reset
None of the above
Answer:
Why:
7
Problem 5:
Based on given VHDL code, sketch the schematic it may infer. Use the symbols
provided in the table if needed based on your analysis of VHDL code.
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIREG is
port (
CLOCK, LE, TRIEN, DIN : in std_logic;
FFOUT, LATCHOUT
: out std_Logic);
end TRIREG;
architecture RTL of TRIREG is
begin
ff0 : process (TRIEN, CLOCK)
begin
if (TRIEN = '0') then
FFOUT <= 'Z';
elsif (CLOCK'event and CLOCK = '1') then
FFOUT <= DIN;
end if;
end process;
latch0 : process (LE, TRIEN, DIN)
begin
if (TRIEN = '0') then
LATCHOUT <= 'Z';
elsif (LE = '1') then
LATCHOUT <= DIN;
end if;
end process;
end RTL;
Tri-state buffer:
Latch:
Flip-flop:
Sketch the schematic here:
8
Problem 6:
You are going to design the following circuit as shown in Fig. 2. Assume the design of
the counter was already implemented and is declared in library “Count_library.lib”, and
in a package “Counter_pkg”.
Package Counter_pkg is
component count
port( clk, en, reset : in bit;
Q : out bit_vector (3 downto 0);
tc : out bit);
end component;
end Counter_pkg;
Build the circuit as in Fig. 2 using this existing component and a process MU to
implement the MUX. Write the VHDL code with all necessary declarations and
references.
clk
mux
clk
Fig. 2: Counter with MUX selection
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Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
entity muxcntr is
port(
);
end muxcntr;
architecture MUXCOUNTER1 of muxcntr is
begin
MU: process (sel )
begin
end process;
end MUXCOUNTER1;
10