Eric Jackowski
734 Proposal FFT Survey
The FFT is an algorithm used by many DSP applications, so I plan to do a survey paper
on the FFT algorithm involving the concepts from class. I will focus the survey on the
use of systolic arrays, pipelining, retiming and unfolding of the FFT algorithm. I will
also look into efficient memory organizations and algorithm transformations for the FFT
algorithm. Along with the above, I would like to present how each technique can
possibly lead to higher performance and lower power. In completion of this survey, I
would like to address some future research that can be done and have a complete
understanding of the best fft for a certain application.
Below are papers I have found that contain the main ideas of the survey.
IEEE
Minimizing the memory requirement for continuous flow FFT implementation: continuous flow mixed
mode FFT (CFMM-FFT)
Design of an efficient variable-length FFT processor
Design and implementation of a parallel real-time FFT processor
Twiddle-factor-based FFT algorithm with reduced memory access
Performance analysis of a 64-point FFT/IFFT block designed for OFDM technique used in WLANs
Easily testable and fault-tolerant FFT butterfly networks
A radix-2 FFT algorithm for modern single instruction multiple data (SIMD) architectures
A delay spread based low power reconfigurable FFT processor architecture for wireless receiver
A low-power and domain-specific reconfigurable FFT fabric for system-on-chip applications
A genetic algorithm for the optimisation of a reconfigurable pipelined FFT processor
New in-place strategy for a mixed-radix FFT processor
A 2048 complex point FFT processor using a novel data scaling approach
A new memory reference reduction method for FFT implementation on DSP
Fast Fourier Transform for high speed OFDM wireless multimedia system
A novel low-power reconfigurable FFT processor
Conflict-free parallel memory access scheme for FFT processors
A coefficient memory addressing scheme for VLSI implementation of FFT processors
A dynamic scaling FFT processor for DVB-T applications
Novel low power pipelined FFT based on subexpression sharing for wireless LAN applications
A new method for accelerating the FFT algorithm in massive image processing
Parallel implementation of 1-D fast Fourier transform without inter-processor communications
A small-area high performance 512-point 2-dimensional FFT single-chip processor
A triple port RAM based low power commutator architecture for a pipelined FFT processor
Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 /spl
mu/m bulk CMOS
General FFT pruning algorithm
A 2048 complex point FFT architecture for digital audio broadcasting system
A hardware efficient control of memory addressing for high-performance FFT processors
Some New Parallel Fast Fourier Transform Algorithms
ACM
High-level low power design II: A VLSI array processing oriented fast fourier
transform algorithm and hardware implementation
Synthesis of pipelined DSP accelerators with dynamic scheduling
Optimizing computations for effective block-processing
Computing the discrete Fourier transform on FPGA based systolic arrays
Chris Dick
Compilation for a high-performance systolic array
High-level low power design II: A VLSI array processing oriented fast fourier
transform algorithm and hardware implementation
FPGA circuits and architectures: Design of a high performance FFT processor
based on FPGA