7. Hazards in Combinational Logic Circuits
7. HAZARDS IN COMBINATIONAL LOGIC CIRCUITS
A hazard is a momentary error condition (a spurious signal or glitch) that occurs in the output
of a combinational logic circuit. Propagation delays in real circuits are responsible for the
momentary error conditions – hazards. If all the elements including the interconnect wiring
used in combinational logic circuits had no delay time, hazards would not exist.
The output signals of combinational logic circuits are normally not available to use until
all the outputs have settled (reached their final steady state values). Hazardous output signal of
combinational logic can cause a problem if it is used to drive a trigger – device of sequential
logic, because even short momentary error signal can set false state of trigger.
7.1. Types of Hazards
Hazards are classified as either static hazards or dynamic hazards. Both static and dynamic
hazards are classified as either function or logic.
7.1.1. Static Hazards
A static hazard occurs when one or more combinational logic circuit input signals change value,
and the final steady state of output value remains the same. A static hazard is logic 0 glitch
(short low level signal in steady high level output signal), or logic 1 glitch (short high level
signal in steady low level output signal).
A static hazard can occur in such simple combinational circuit as single two inputs' gate.
Let us see, how static hazard occurs in output of 2AND. According the definition gate inputs'
signals ought to change, while output signal must remain the same. So it happens when signal
in one input changes from 0 to 1, while signal in another input changes from 1 to 0. In real
circuit the input signals cannot occur simultaneously, one input signal always is less or more
delayed with respect to another.
As we can see from the picture, the logic 1
A
A
glitch occurs in output of the gate when signal A
F
B
B
in input B is delayed with respect to signal in B 
F
F
input A (case b). Otherwise (case a) the error
signal does not occur.
a
b
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7. Hazards in Combinational Logic Circuits
Now we can formulate an important conclusion: hazard is not an error; it is only a risk of
error. Condition, that static hazard occurs when input signals change value, and output value
remains the same, is necessary error condition, but it is not sufficient. Another condition must
be fulfilled: delay times of signals in inputs must be unfavourable.
Example 7.1
Draw time diagrams, illustrating, when static hazard in output of 2OR gate becomes an error, and when it does
not become an error.
7.1.2. Dynamic Hazards
A dynamic hazard occurs when there is a realized static hazard (logic 0 glitch or logic 1 glitch)
in one or more input and the value of output signal changes. Dynamic hazard is broken 0-to-1
transition or broken 1-to-0 transition.
Time diagrams on the picture illustrate, how dynamic hazard – broken 0-to-1 transition –
occurs in the output of 2OR gate.
A
Like in the case of static hazard, dynamic hazard
A
F
B
1
becomes an error, when delay times of signals in inputs
B
F
are unfavourable.
t1 t2
t
Example 7.2
Draw time diagrams, illustrating the case, when dynamic hazard in
output of 2OR gate does not become an error.
Example 7.3
Draw time diagrams, illustrating the case, when dynamic hazard becomes an error in output of 2AND gate.
7.1.3. Function Hazards
A hazard that can be caused in the output signal, when more than one input signal is changed
simultaneously, is called a function hazard. A function hazard can be spotted in the Karnaugh
map. We will illustrate this on the
A BC
example of a definite logic func00
01
11
10
tion F(A,B,C), filled in Karnaugh
1
0
1
0
0
F
map on the picture.
0
1
0
1
1
F
Time diagram a illustrates
1
A C  00  A C  11
the case, when two logic variabStatic function hazard – 0
a
000  101
00
glitch
les A and C change values from 0
A C  10  A C  01
1
to 1 (AC  0011). This change
Static function hazard – 1
b
100  001
glitch
of values of logic variables cor0
responds to transition from
A BC  000  A BC  111 1
c
Dynam ic function hazard – 1-to000  111
square 000 to square 011 in Kar0
0
naugh map. There are two ways
A BC  100  A BC  011 1
d
Dynam
ic
function
hazard
–
0-to100  011
from square 000 to square 011:
0
1
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7. Hazards in Combinational Logic Circuits
across the square 001, when 1 in input A is delayed with respect to 1 in input B, and across the
square 010, when 1 in input B is delayed with respect to 1 in input A. In both cases value of
function changes from 1 to 0 and from 0 to 1.
Example 7.4
Explain time diagrams b, c, and d.
7.1.4. Logic Hazards
A hazard that can be caused in the output signal, when only one input signal changes, is called a
logic hazard. A logic hazard can be spotted in the Karnaugh map too. A logic hazard occurs
when there are two 1s in adjacent squares of Karnaugh map, and they are in different circles of
1s.
A BC
00
01
11
10
We will illustrate it by analysis of definite logic
function F(A,B,C) filled in Karnaugh map on the
1
0
F
picture.
1
1
1
1
p2
According the Karnaugh map we can write
p1
minimized SOP expression of the function:
a
F = p1 + p2 = AC + BC.
A 11
X 10
F

1
In accordance with definition of a logic hazard, C 1 0
the hazard can occur with transition from square 111
B 11
Y 01
to square 110 in Karnaugh map. We will analyze this

C 1 0
C 01
transition in the logic diagram that realizes the mini1
b
mized SOP expression of the function. The transition
from square 111 to square 110 corresponds with such values of logic variables: A  11;
B  11; C  10 (only one logic variable changes its value). The inverter in input C is the
reason why signal Y is delayed with respect to signal X, and this delay causes the spurious 0
glitch in the output F.
7.2. Design of Hazard-Free Combinational Circuits'
There is no possibility to design a function hazard-free combinational circuit. The designer of
the combinational circuit has merely one way: to avoid an unfavourable delay times in the
inputs of gates. The other ways are:
– to forbid change of values in two and more inputs simultaneously;
– to avoid an influence of momentary errors on functioning of logic circuit by synchronizing the circuit: during the elementary cycle all output signals in the circuit must settle in
steady state;
– if the combinational circuit drives triggers, the triggers with enable inputs ought to be
used; the enable signal must occur when all outputs of combinational logic circuit are in steady
state.
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7. Hazards in Combinational Logic Circuits
It is possible and it is necessary to design a logic hazard-free combinational circuit. To
eliminate logic hazards use the following two-step procedure:
– obtain a minimum covering of 1s by circles in Karnaugh map;
– cover by additional circles the 1s in adjacent squares of Karnaugh map, that are in
different circles of 1s.
We will illustrate this procedure by analysis of the
A BC
00
01
11
10
circuit with logic hazard from section 7.1.4.
1
0
The additional circle in Karnaugh map is circle p3. The
F
logic diagram that realizes new expression of logic function is
1
1
1
1
p2
shown in picture b. The additional 2AND gate in logic diagram
p3
p1
a
with inputs A and B corresponds to additional product p3  AB
F  1 in expression of logic function. This gate creates a stable 1 in

1
its output, and eliminates possibility of logic hazard in output
of the NOR gate – in output of the circuit.

1
A 11
B 11

Z 11
b
CONTROL QUESTIONS AND PROBLEMS
7.0.1. What is a hazard in combinational logic?
7.0.2. Show the main reason of hazards in combinational logic.
7.0.3. Name the ways to avoid hazards in combinational logic – logic without triggers.
7.1. Types of Hazards
7.1.1. How do the hazards in combinational logic are classified?
7.1.2. When does the possibility of static hazard occur? Draw the diagrams of signals in input and in output of
2NAND gate for two cases: for case when hazard became error, and for opposite case. Name this hazard.
7.1.3. When does the possibility of dynamic hazard occur? Draw the diagrams of signals in input and in output
of 2NOR gate for two cases: for case when hazard became error, and for opposite case. Name this hazard.
7.2. Design of Hazard-Free Combinational Circuits'
7.2.1. Draw the circuit from available gates that realizes logic function F(A,B,C) =  m(1,3,4,5) without risk of
logic error.
7.2.2. How many logic errors can occur in the circuit that realizes logic function F(A,B,C,D) =  m(0,1,2,5,6,
7,15), written according minimum quantity of circles in Karnaugh map?
7.2.3. Logic function F(A,B,C,D) =  m(0,2,4,5,6,7,8,10,11,15) write in SOP form that guarantees operating of
logic circuit without logic errors.
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