AOI-22 design
Introduction
This report studies the design of AOI-22 function. It shows the De'morgan analysis,
the truth table, schematic figure, the stick diagram, drawn layout using L-edit and the
output signals simulated by A/D Pspice.
The function
The function to be analyzed is AOI-22 (and-or-invert) with two of two-input and
gates Ored together with a Nor gate.
The technology used is 0.5um (Lambda = 0.35um).
Here is a gate schematic of the function:
De'morgan Analysis
F(x) = (A.B+C.D)' = (A.B)'.(C.D)' = (A'+B').(C'+D')
The truth table
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F(x)
1
1
1
0
1
1
1
0
1
1
1
0
0
0
0
0
The transistor schematic figure
The stick diagram
AOI-22 layout
The extraction file
* Circuit Extracted by Tanner Research's L-Edit Version 8.30 / Extract
Version 8.30 ;
* TDB File: G:\AOI-22.tdb
* Cell: Cell0
Version 1.03
* Extract Definition File: C:\Tanner\LEdit83\Samples\tech\mosis\mhp_n05.ext
* Extract Date and Time: 12/17/2004 - 15:45
* NODE NAME ALIASES
*
1 = VDD (20,53)
*
3 = out (46.5,26.5)
*
4 = VSS (20,13)
*
8 = B (24.5,28.5)
*
9 = C (32.5,29.5)
*
10 = D (40.5,29.5)
*
12 = A (16.5,29)
M8 1
* M8
M7 2
* M7
M6 3
* M6
M5 2
* M5
M4 7
* M4
M3 4
* M3
M2 5
* M2
M1 3
* M1
12 2 11 PMOS L=2u W=5u AD=15p PD=11u AS=27.5p PS=21u
DRAIN GATE SOURCE BULK (15.5 37 17.5 42)
10 3 11 PMOS L=2u W=5u AD=27.5p PD=21u AS=15p PS=11u
DRAIN GATE SOURCE BULK (39.5 37 41.5 42)
9 2 11 PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u
DRAIN GATE SOURCE BULK (31.5 37 33.5 42)
8 1 11 PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u
DRAIN GATE SOURCE BULK (23.5 37 25.5 42)
12 4 6 NMOS L=2u W=5u AD=5p PD=7u AS=27.5p PS=21u
DRAIN GATE SOURCE BULK (19.5 17 21.5 22)
10 5 6 NMOS L=2u W=5u AD=27.5p PD=21u AS=5p PS=7u
DRAIN GATE SOURCE BULK (35.5 17 37.5 22)
9 3 6 NMOS L=2u W=5u AD=5p PD=7u AS=15p PS=11u
DRAIN GATE SOURCE BULK (31.5 17 33.5 22)
8 7 6 NMOS L=2u W=5u AD=15p PD=11u AS=5p PS=7u
DRAIN GATE SOURCE BULK (23.5 17 25.5 22)
Vdd 1 0 dc 5
Vss 4 0 dc 0
Va 12 0 PULSE (0 5 0N 1N 1N 200N 400N)
Vb 8 0 PULSE (0 5 0N 1N 1N 100N 200N)
Vc 9 0 PULSE (0 5 0N 1N 1N 50N 100N)
Vd 10 0 PULSE (0 5 0N 1N 1N 25N 50N)
.MODEL PMOS pmos level=2 nsub=4e15 tox=50n
.MODEL NMOS nmos level=2 nsub=4e15 tox=50n
.TRAN 10N 500N
.probe
* Total Nodes: 12
* Total Elements: 8
* Total Number of Shorted Elements not written to the SPICE file: 0
* Extract Elapsed Time: 0 seconds
.END
Propagation delay
At 50% of input, t = 126.5 ns
At 50% of output, t = 126.7 ns
Propagation delay = 126.7n – 126.5n = 0.2n sec
Rise time
At 90% (0.5 V), t = 226.448 ns
At 10% (4.5 V), t = 226.961 ns
Rise time, tr = 0.513 ns.
Fall time
At 10% (4.5 V), t = 300.537 ns
At 90% (0.5 V), t = 300.984 ns
Fall time, tf = 0.447 ns.
Power dissipation
From output file:
VOLTAGE SOURCE CURRENTS
NAME
CURRENT
Vdd
Vss
Va
Vb
Vc
Vd
-9.702E-12
9.702E-12
0.000E+00
0.000E+00
0.000E+00
0.000E+00
TOTAL POWER DISSIPATION
4.85E-11
WATTS