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Objectives:
A. Examine the sampling process of the PCM encoder circuit.
B. Demonstrate the quantization process of the PCM encoder circuit.
C. Determine the coding process of the PCM encoder circuit
Basic Concepts
1. The pulse-code modulation encoding process samples an intelligence signal, quantizes the sampled intelligence signal and codes the quantized intelligence signal into binary-coded digits.
2. Sampling is the process of obtaining an instantaneous value of the intelligence signal amplitude at regular intervals.
3. Quantization is the process of converting the voltage level of the sampled amplitude to the voltage value of the nearest standard level, or quantum.
4. Coding is the process of representing a particular quantum of the analog signal with a binary code.
5. The minimum rate at which samples may be taken is called the Nyquist rate.
Introductory Information
Block diagram of a PCM encoder circuit is shown in Figure 1. Its operation depends on three separate processes - sampling , quantization and coding . It is the function of a PCM encoder circuit to make provision for each of these processes.
Sampling occurs at the sample/hold circuit. The sample/hold circuit stores the value of the intelligence signal sample until the circuit is commanded to store a new value. Quantization occurs at the ADC circuit. The total range that the intelligence signal amplitude covers is divided by the ADC into a number of standard levels, called quantum. The ADC determines the quantum of the sampled value of the intelligence signal and assigns the voltage of that quantum to the sampled amplitude of the intelligence signal. The coding process occurs in the
ADC circuit and the parallel-to-serial converter. The voltage of the quantized signal is converted into digital data by the ADC and sent to a transmitter serially (one bit at a time) by the parallel-to-serial converter. The serial data stream represents the PCM signal. The timing signal generator supplies clock signals to the ADC and parallel-to-serial converter and pulses to the sample/hold circuit, ADC and parallel-to-serial converter. The clock signals and pulses are used to synchronize the PCM encoder circuit.
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Equipment
Power Source: + 15Vdc, l50mA
Power Source: 15Vdc, 50mA
Dual Trace Oscilloscope
Audio Frequency (AF) Generator
Pulse-Code Modulation Trainer
Figure 1
Procedures
Objective A: Examine the sampling process of the PCM encoder circuit.
Preparatory Information
The sample/hold circuit stores the value of the intelligence signal at the command of an enable pulse and holds the stored value at the circuit’s output until the circuit is commanded to store a new value. The result is the sampled intelligence signal shown in Figure 2. Each step of the signal represents the instantaneous amplitude of the intelligence signal at the sampling interval.
Figure 2
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The frequency of the enable pulse is the sampling signal. In PCM, the sampling signal frequency (fs) is twice the maximum intelligence signal frequency (fm), called the Nyquist rate. The sampling signal frequency of the sample/hold circuit must be equal to or greater than the Nyquist rate. This is expressed by the equation: fs = 2(fm) where fs = sampling signal frequency and fm = maximum intelligence signal frequency. For example, a sampling signal frequency of 8kHz will accurately reproduce a signal with a maximum frequency of 800kHz. The Nyquist rate is fs = 2(fm) = 2(800Hz) = 1.6kHz. The sampling rate of 8kHz is larger than the Nyquist rate of 1.6kHz, so the signal will be accurately reproduced. The original intelligence signal cannot be accurately reproduced if the sampling signal frequency is less than the Nyquist rate.
The sample/hold circuit schematic is shown in Figure 3. The sample/hold circuit of the PCM
ENCODER receives the intelligence signal at J37. An enable pulse from the timing signal generator at J43 is input to the sample/hold circuit. The enable pulse allows the intelligence signal to be sampled. The sampled signal at J38 is held until the next enable pulse is received.
Figure 3
Experimental procedures a) Three different voltage levels are to be supplied to the trainer board, i.e. +15Vdc, -15Vdc, and 0V (ground). You MUST ensure that correct voltage levels and polarities will be applied accordingly. To avoid any mistake, you can first verify the correctness by, for example, using the oscilloscope to probe the respective voltage levels. Now connect the +15Vdc, -15Vdc, and
0V (ground) ports of the supply voltage across the +15V, -15V, and GND (ground) terminals of the PCM board, RESPECTIVELY.
NOTE: Check your connections and then apply power to the trainer. Test the power supply
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inputs on the trainer to be sure the proper voltages and polarities are applied to the trainer. Turn off the power. b) Connect the circuit shown in Figure 4 using jumper wires to interconnect the jacks on the trainer. Keep the connections throughout the experiment.
Apply power to the trainer.
Figure 4 c) Set both oscilloscope probes to a x1 setting. Set the channel 1 attenuator to 2V/cm, sweep speed to 20
 s/cm and use the dc mode. If there is a ‘Var Sweep’ knob on the oscilloscope, turn it fully clockwise. Set the SYMM ADJ control on the PCM encoder circuit fully clockwise. d) Connect the channel 1 probe to J39. Adjust the SCALE ADJ control so that a 5Vp-p, 16 quantum signal is displayed. Set the ZERO ADJ control at the center of rotation. Set the
SYMM ADJ control so there are 7 steps in the quantum signal at J39. J39 signal will be discussed in the latter experiment. e) Connect the AF generator to the channel 1 probe of the oscilloscope. Adjust the AF generator frequency to 800Hz and set the AF level control to produce a 3Vp-p sine wave.
Now connect the AF generator to J37. Use the channel 1 probe of the oscilloscope to monitor the signal. What does the signal at J37 represent?
Answer: The 3Vp-p, 800Hz signal input at J37 represents the __________ signal. f) Set the oscilloscope to a sweep speed of 0.2ms/cm. Connect the channel 2 probe to J38.
Trigger the oscilloscope on channel 1. Observe the signals at J37 and J38 at the same time.
Compare the two signals and explain their relationship.
Answer: The signal at J38 represents the _______________ signal.
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g) Remove the channel 1 probe from J37 and connect them to J43. Set the intensity of the oscilloscope to maximum. Observe the signal at J43 and record its frequency. f = …………kHz
Confirm that the signal at J43 is a series of narrow, positive pulses of 5Vp-p, with a frequency of 8kHz. What is the function of the signal at J43?
Answer: The signal at J43 functions as the __________ signal. h) Trigger the scope on channel 2. You will see that each sample of the signal at J38 (channel
2) starts on a pulse from the signal at J43 (channel 1). i ) Turn off the power supply and AF generator. Disconnect the AF generator. Keep the circuit connections.
___________________________________________________________________________
Objective B: Demonstrate the Quantization Process of the PCM encoder Circuit.
Preparatory Information
The ADC divides the total range of the intelligence signal into a number of quantum levels.
The number of quantum levels depends on the number of output bits in the ADC circuit. The formula is: L = 2 n , where L is the number of quantum levels and n is the number of bits.
For example, if a 2-bit ADC ( n =2) is used the number of quantum levels L = 2
2
= 4.
The voltage difference between two quantum levels is called the step size. The step size depends on the total range of the sampled amplitude and the number of quantum. The equation for finding the step size of the quantum is:
Vss = Vfsr/(L-1), where Vss = step size voltage
Vfsr = full-scale range voltage
L = number of quantum levels
For example, the step size of a 6V quantized signal from a 2-bit ADC is 2V.
Vss = Vfsr/(L-1)
Vss = 6V/(4-1)
Vss = 2V
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In the quantization process the amplitude of the sampled intelligence signal will fall on or between two quantum levels. The voltage value of the lesser quantum is the amplitude of the sampled intelligence signal. The sampled intelligence signal and quantized signal from a 2-bit
ADC are shown in Figure 5.
Figure 5
The 2-bit ADC generates a four quantum output, quantum 0-3. When the intelligence signal amplitude is 4.2V, the quantized output is not represented as 4.2V amplitude. The amplitude of 4.2V falls between the 4.0V value of quantum 2 and the 6.0V value of quantum 3. Since the 4.0V value of quantum 2 is the lesser quantum it becomes the amplitude of the sampled intelligence signal. In the ADC circuit of the PCM ENCODER (Figure 3) the count and the reference signal begin as zero.
The comparator receives the sampled amplitude of the intelligence signal at J38 and compares it to the reference signal from the DAC at J39. When the amplitude of the intelligence signal is greater than zero, a positive output from the comparator will enable the counter. The timing signal generator applies a clock signal at J41 to advance the count. As the count starts an output of 0001 appears at B3 – B0 and 0001 is sent to the DAC. The DAC converts the count of 0001 into an analog value, which is sent to the comparator as a reference signal. This process continues for as long as the sampled amplitude is greater than the reference signal.
Once the count reaches a point where the sampled amplitude is less than or equal to the reference signal the negative output of the comparator disables the counter. The reference signal from the DAC remains at its present value until the counter is reset by a negative pulse applied to its CLEAR input. The reference signal from the DAC output represents the quantum of the sampled amplitude. At this point the quantization process is complete for that sample. The quantization process continues in this manner for the remainder of the intelligence signal. The timing signal generator applies a pulse at J44 to reset the counter after sixteen counts.
Experimental procedures a) With the same circuit connections as shown in Figure 4, turn on the power supply.
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b) Set the oscilloscope for a sweep speed of 20
 s/cm. Connect the channel 1 probe to J38 and the channel 2 probe to J39. Set the SYMM ADJ control fully clockwise. Observe the signal at J39. The 5Vp-p signal at J39 is the total range voltage . What does the signal at J39 show?
Answer: The ___ quantum levels shown in the signal at J39 are the maximum number of quantum that can be generated by the circuit. c) Set the SYMM ADJ control to output a 4V signal at J38. Observe the signal. The signal at
J38 represents a sample amplitude of 4V. d) Examine the signal at J39. Describe the signal.
Answer: The signal at J39 is a 4Vp-p, ___ quantum signal. e) The total range voltage of the PCM encoder circuit is 5Vp-p. Calculate the step size.
Answer: There are 16 quantum levels. The step size is thus _____ V. f) Observe the quantized signal with a total range of 5Vp-p and 16 quantum levels on the graph provided in Figure 6. Label the voltage value of each quantum. In what quantum level would a sample amplitude of 4V fall?
Figure 6
Answer:
Quantum Voltage value Quantum Voltage value Quantum Voltage value
0
1
5
6
10
11
2
3
4
7
8
9
Sample amplitude of 4V would fall in quantum _____.
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13
14
15
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g ) Adjust the SYMM ADJ control for 7 quantum steps at J39. Apply power to the AF generator. Adjust the AF generator frequency to 800 Hz and the AF level control to produce a
3Vp-p sine wave (as in the previous setting). Connect the AF generator to J37. The signal at
J37 now represents the original intelligence signal. h ) Set the oscilloscope to a sweep speed of 1 ms/cm. Move the channel 1 probe to J38. Using the channel 1 position control move the sampled intelligence signal at J38 to cover the quantized signal at J39. Compare the signals. Are they the same?
Answer: _____ i ) Turn off the power supply and AF generator. Disconnect the AF generator. Keep the circuit connections.
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Objective C. Determine the coding process of the PCM encoder circuit
Preparatory Information
The ADC converts the quantized signal into a parallel output of binary-coded digits, or bits
(Figure 7). This parallel digital output is called a binary word, or data. The data is transferred to a parallel-to-serial converter. The parallel-to-serial converter outputs one bit of data at a time. The most significant bit (msb) is output first and the least significant bit (lsb) last
(Figure 8).
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Figure 7 Figure 8
The data is then serial-transferred to the transmitter. The clock rate (fc) is the rate at which the data is output from the parallel-to-serial converter. The clock rate is equal to the number of bits in the ADC output times the sampling signal frequency. The equation for finding the clock rate is: fc = (n) (fs), where fc = clock rate n = number of bits fs = sampling signal frequency
For example, an encoder having a sampling signal frequency of l0 kHz and a 2-bit ADC has a clock rate of 20 kHz. fc = (n) (fs) = (2) (10 kHz) = 20 kHz
The baud rate (R) is a unit of signaling speed equal to the number of bits transferred per second. In PCM, one baud is equal to one bit per second. A PCM output signal is shown in
Figure 9.
Figure 9
The bit time (Tb) of the signal is the pulse width of one bit. The baud rate of the signal is equal to the inverse of the bit time:
R = 1/Tb where R = baud rate
Tb = bit time
For example, a signal with a 50micro-second bit time will have a baud rate of 20 kilobaud.
R = 1/0.00005 = 20 kilobaud
The clock signal to the parallel-to-serial converter is also shown in Figure 9. Each bit of the
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PCM signal begins on each leading edge of the clock signal. Therefore, one bit is transferred for each clock cycle. Therefore, the number of bits transferred per second is equal to the number of clock cycles per second. This makes the baud rate equal to the clock rate.
The coding process begins at the ADC circuit and ends at the parallel-to-serial converter of the PCM ENCODER circuit (Figure 3). When the quantization of one sample is complete, the output of the 4-bit synchronous counter is the coded value of the quantum of the sampled amplitude. The coded value is shown as a parallel output of a binary word. The binary word is stored in the register. The timing signal generator applies an enable pulse to the register at
J43. The enable pulse transfers the binary word from the register to the parallel-to-serial converter. Each bit of the binary word is output at B3 – B0, with B3 being the msb. The timing signal generator sends an enable pulse to the load/shift input at J44. This loads the binary word into the parallel-to-serial converter. When the pulse at the load/shift input is removed, the serial shift is enabled. The timing signal generator applies a clock signal at J42 to shift out each bit serially.
Experimental procedures a) With the same circuit connections as shown in Figure 4, turn on the power supply. Set the oscilloscope sweep speed to 20
 s/cm. Move the channel 1 probe to J38. Move the channel 2 probe to J39. b) Set the SYMM ADJ control for a 5V signal at J38. Set the SCALE ADJ control for a
5Vp-p, 16 quantum signal at J39. Reset the SYMM ADJ control for a 3V signal at J38. c) Observe the signal at J39. Into what quantum does the sampled amplitude of 3V fall?
Answer: The sampled amplitude of 3V falls into the _____ quantum. d) Connect the channel 1 probe to output B3. Observe and record the voltage of the signal at
B3. Repeat this process for outputs B2, B1, and B0. What is the decimal equivalent of outputs
B3-B0. Compare those outputs with the output at J39.
Answer: B3-B0 give binary value of _____, which means _____ in decimal. These outputs are equal to the number of quantum in the signal at J39. They represent the parallel, binary-coded digits output from the register of the ADC. e) Set the intensity control of the oscilloscope to maximum. Move the channel 1 probe to J40.
Move the channel 2 probe to J43. Using the channel 1 position control move the signal at J40 to cover the signal at J43. Identify the signal at J40. What is its relationship to outputs of
B3-B0?
Answer: The signal at J40 is a series of bits representing the word _____. The parallel
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binary-coded digits of B3-B0 have been converted into the serial data at J40. f) Move channel 2 to J42. Measure and record the frequency.
Answer: f = _____ kHz. g) Calculate the clock rate needed at the parallel-to-serial converter for data transmission. Is it the same as the frequency at J42?
Answer: The number of bits is ___. The sampling rate is ___ kHz. Therefore the clock rate needed is _____ kHz, __________ to the frequency at J42. J42 signal is used as the _____ signal to parallel-to-serial converter.
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Summary
In this laboratory exercise you examined the sampling process of the PCM encoder circuit.
The sampled intelligence signal and the enable pulse were both observed. It was determined that each sample begins on the enable pulse. You demonstrated the quantization process of the
PCM encoder circuit. The voltage value of a quantum was determined and the sampled signals and quantized signals were compared. You observed the coding process of the PCM encoder circuit. It was found that the binary-coded signal is the binary equivalent of the quantum. Also, you observed that the parallel digital signal of the ADC is converted into a series of bits that are transmitted. The clock frequency for the parallel-to-serial converter was determined.
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