Background Statement for SEMI DRAFT Document 4624A (rev. 15)
NEW STANDARD: SPECIFICATION FOR DEVELOPMENTAL 450 mm
DIAMETER POLISHED SINGLE CRYSTAL SILICON WAFERS
Note: This background statement is not part of the balloted item. It is provided solely to assist the
recipient in reaching an informed decision based on the rationale of the activity that preceded the creation
of this document.
Note: Recipients of this document are invited to submit, with their comments, notification of any relevant
patented technology or copyrighted items of which they are aware and to provide supporting
documentation. In this context, “patented technology” is defined as technology for which a patent has
issued or has been applied for. In the latter case, only publicly available information on the contents of
the patent application is to be provided.
Attached document specifies 450 mm diameter polished single crystal wafers intended for use
in research and development of process and metrology equipment and fabrication processes
required to manufacture high-density integrated circuits on 450 mm diameter single crystal
silicon wafers. It can also be used to establish the techniques and metrology necessary to
support a dimensional specification for 450 mm diameter circuit-quality (prime) wafers.
This document should be superseded by dimensional specification and technology-specific guidelines
for circuit-quality wafers.
The detailed specifications for 450 mm wafers are organized in three categories to assist manufacturers
in choosing the most cost effective wafers for a given application:
Particle monitors, intended for use in evaluating the particle contamination added by a process tool.
Lithography monitors, for development of lithographic and patterning equipment and processes.
Other monitors, suitable for use in process and inspection equipment development (other than particle
counting or lithography development).
The developmental wafers dimensional requirement are identical to the 450 mm mechanical handling
wafers, published in SEMI M74, except wafer diameter tolerance, tightened to +/- 0.1 mm, to better
reflect wafer handling and some process equipment needs.
When specifying the wafer edge profile the customers must select one of two options, a parameter
based profile or a template based edge profile.
The results of this document will be reviewed at the Int’l 450 mm Wafer TF and will be adjudicated by
the Japan Silicon Wafer committee during their meetings at SEMICON Japan in December 2-4, 2009 in
Makuhari Messe, Chiba, Japan. Please check www.semi.org/standards for the latest meeting schedule.
DRAFT
Document Number: 4624A
Date: 2/13/2016
SEMI DRAFT Document 4624A
NEW STANDARD: SPECIFICATION FOR DEVELOPMENTAL 450 mm
DIAMETER POLISHED SINGLE CRYSTAL SILICON WAFERS
1 Purpose
1.1 The developmental wafers covered by this specification are intended for use in research and development of
process and metrology equipment and fabrication processes required for manufacturing high-density integrated
circuits on 450 mm diameter single crystal silicon wafers. They can also be used to establish the techniques and
metrology necessary to support a dimensional specification for 450 mm diameter circuit-quality (prime) wafers.
2 Scope
2.1 This specification covers dimensional and crystallographic orientation requirements for 450 mm diameter,
polished single crystal silicon wafers needed in development. This document should be superseded by dimensional
specification and technology-specific guidelines for circuit-quality wafers.
2.2 A complete purchase specification requires that additional physical properties be specified along with test
methods for determining their magnitude. If a test instrument is not available, the acceptance criteria should be
agreed upon between supplier and customer.
2.3 This specification also contains guidance to assist equipment manufacturers and others to specify wafers for use
in developing selected process equipment and unit processes.
2.4 The specification for 450 mm diameter mechanical handling wafers used in development of 450 mm
semiconductor equipment such as 450 mm wafers carriers, load ports, Automated Materials Handling System
(AMHS), and robotics has already been published as SEMI M74.
2.5 This specification is not intended to be a product wafer specification.
2.6 For referee purposes, SI (System International, commonly called metric) units shall be used.
NOTICE: This standard does not purport to address safety issues, if any, associated with its use. It is the
responsibility of the users of this standard to establish appropriate safety and health practices and determine the
applicability of regulatory or other limitations prior to use.
3 Referenced Standards and Documents
3.1 SEMI Standards
SEMI E45 — Test Method for the Determination of Inorganic Contamination from Mini Environments Using Vapor
Phase Decomposition-Total Reflection X-ray Spectroscopy (VPD/TXRF), VPD-Atomic Absorption Spectroscopy
(VPD/AAS), or Inductively Couples Plasma-Mass Spectroscopy (VPD/ICP-MS)
SEMI M1 — Specifications for Polished Single Crystal Silicon Wafers
SEMI M12 — Specification for Serial Alphanumeric Marking of the Front Surface of Wafers
SEMI M13 — Specification for Alphanumeric Marking of Silicon Wafers
SEMI M20 — Practice for establishing a wafer coordinate system
SEMI M33 — Test Method for the Determination of Residual Surface Contamination on Silicon Wafers by Means
of Total Reflection X-Ray Fluorescence Spectroscopy (TXRF)
SEMI M43 — Guide for Reporting Wafer Nanotopography.
SEMI M49 — Guide for Specifying Geometry Systems Equipment forSilicon Wafers for the 130 nm to 22 nm
Technology Generations.
SEMI M52 — Guide for Specifying Scanning Surface Inspection Systems for Silicon Wafers for the 130 nm, 90
nm, 65 nm, and 45 nm Technology Generations
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted standard. Permission is granted to
reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other
reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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SEMI M53 — Practice for Calibrating Scanning Surface Inspection Systems Using Certified Depositions of
Monodisperse Reference Spheres on Unpatterned Semiconductor Wafer Surfaces
SEMI M58 — Test Method for Evaluating DMA-Based Particle Deposition Systems and Processes
SEMI M59 — Terminology for Silicon Technology.
SEMI M67 — Practice for Determining Wafer Near-Edge Geometry from a Measured Thickness Data Array Using
the ESFQR, ESFQD and ESBIR Metrics
SEMI M68 — Practice for Determining Wafer Near-Edge Geometry from a Measured Height Data Array Using a
Curvature Metric, ZDD
SEMI M70 — Practice for Determining Wafer-Near-Edge Geometry Using Partial Wafer Site Flatness
SEMI M73 — Test method for Extracting Relevant Characteristics from Measured Wafers Edge Profiles
SEMI M74 — Specifications for 450 mm Diameter Mechanical Handling Polished Wafers
SEMI MF26 — Test Methods for Determining the Orientation of a Semiconductive Single Crystal
SEMI MF42 — Test Methods for Conductivity Type of Extrinsic Semiconducting Materials
SEMI MF81 — Test Method for Measuring Radial Resistivity Variation on Silicon Wafers
SEMI MF523 — Practice for Unaided Visual Inspection of Polished Silicon Wafer Surfaces
SEMI MF533 — Test Method for Thickness and Thickness Variation of Silicon Wafers
SEMI MF534 — Test Method for Bow of Silicon Wafers
SEMI MF657 — Test Method for Measuring Warp and Total Thickness Variation on Silicon Wafers by Noncontact
Scanning
SEMI MF673 — Test Methods for Measuring Resistivity of Semiconductor Wafers or Sheet Resistance of
Semiconductor Films with a Noncontact Eddy-Current Gage
SEMI MF951 — Test Method for Determination of Radial Interstitial Oxygen Variation in Silicon Wafers
SEMI MF1049 — Practice for Shallow Pit Detection on Silicon Wafers
SEMI MF1152 — Test Method for Dimensions of Notches on Silicon Wafers
SEMI MF1188 — Test Method for Interstitial Atomic Oxygen Content of Silicon by Infrared AbsorptionWith Short
Baseline.
SEMI MF1366 — Test Method for Measuring Oxygen Concentration in Heavily Doped Silicon Substrates by
Secondary Ion Mass Spectrometry
SEMI MF1389 — Test Method for Photoluminescence Analysis of Single Crystal Silicon for III-V Impurities.
SEMI MF1390 — Test Method for Measuring Warp on Silicon Wafers by Automated Noncontact Scanning
SEMI MF1451 — Test Method for Measuring Sori on Silicon Wafers by Automated Noncontact Scanning
SEMI MF1530 — Test Method for Measuring Flatness, Thickness, and Thickness Variation on Silicon Wafers by
Automated Noncontact Scanning
SEMI MF1617 — Test Method for Measuring Surface Sodium, Aluminum, and Potassium on Silicon and Epi
Substrates by Secondary Ion Mass Spectrometry
SEMI MF1619 — Test Method for Measurement of Interstitial Oxygen Content of Silicon Wafers by Infrared
Absorption Spectroscopy with p-Polarized Radiation Incident at the Brewster Angle
SEMI MF1621 — Practice for Determining Positional Accuracy Capabilities of a Scanning Surface Inspection
System
SEMI MF1727 — Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted standard. Permission is granted to
reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other
reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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DRAFT
Document Number: 4624A
Date: 2/13/2016
SEMI MF1810 — Test Method for Counting Preferentially Etched or Decorated Surface Defects in Silicon Wafers.
SEMI MF2074 — Guide for Measuring Diameter of Silicon and Other Semiconductor Wafers
SEMI T3 — Specifications for Wafer Box Labels
SEMI T7 — Specification for Back Surface Marking of Double-Side Polished Wafers with a Two-Dimensional
Matrix Code Symbol
3.2 ANSI Standard1
ANSI/ASQC Z1.4 — Sampling Procedures and Tables for Inspection by Attributes
3.3 ASTM Standard2
ASTM E122 — Standard Practice for Choice of Sample Size to Estimate the Average Quality of a Lot or Process
3.4 ISO Standard3
ISO 17331 — Surface Chemical Analysis — Chemical methods for collection of elements from the surface of
silicon-wafer working reference materials and their determination by total-reflection X-ray fluorescence (TXRF)
spectroscopy
4 Terminology
4.1 Terms and acronyms associated with silicon wafers and silicon technology are listed and defined in SEMI M59.
5 Wafer Ordering Information
5.1 Purchase orders for silicon wafers furnished to this specification shall include the following items. Values for
these items are given in Tables 1 and 2.
5.1.1 Developmental wafer monitor category
5.1.2 Crystal Growth Method (see ¶ 6.4).
5.1.3 Conductivity Type and Dopant.
5.1.4 Resistivity or Resistivity Range.
5.1.5 Wafer edge profile type requested (see ¶ 6.5.7).
5.1.6 Lot Acceptance Procedures (see § 7).
5.1.7 Test methods for specified attributes (see § 8).
5.1.8 Certification (if required) (see § 9).
5.1.9 Packing and Package Labeling (see § 10).
5.2 Optional Criteria — The following items may also be specified in addition to those listed above if they are
considered to be necessary for the application for which the wafers are to be employed (see Table 1).
5.2.1 Wafer identification mark symbol or symbols.
5.2.2 Wafer dimensional characteristics requirements — As specified in Appendix 1 of SEMI M1.
5.2.3 Particulate contamination (localized light scatterer) requirements (see ¶ 6.6.2).
1
American National Standards Institute, Headquarters: 1819 L Street, NW, Washington, DC 20036, USA. Telephone: 202.293.8020; Fax:
202.293.9287. New York Office: 11 West 42nd Street, New York, NY 10036, USA. Telephone: 212.642.4900; Fax: 212.398.0023;
http://www.ansi.org
2
American Society for Testing and Materials, 100 Barr Harbor Drive, West Conshohocken, Pennsylvania 19428-2959, USA. Telephone:
610.832.9585; Fax: 610.832.9555; http://www.astm.org
3
International Organization for Standardization, ISO Central Secretariat, 1 rue de Varembé, Case postale 56, CH-1211 Geneva 20, Switzerland.
Telephone: 41.22.749.01.11; Fax: 41.22.733.34.30; http://www.iso.ch
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted standard. Permission is granted to
reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other
reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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SEMI MF1809 — Guide for Selection and Use for Etching Solutions to Delineate Structural Defects in Silicon
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Document Number: 4624A
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5.3 Additional Criteria — Any additional criteria considered to be necessary for the application for which the
wafers are to be employed may also be specified, as agreed between supplier and customer (see Table 1).
6 Requirements
6.1 Table 1 and Table 2 contain detailed specifications for 450 mm diameter wafers intended for use in
development. The requirements are organize by wafer categories and wafer type. Table 1 details wafer required
properties by category to assist manufacturers in choosing the most cost effective wafers for a given application.
Table 2 specifies the different wafer types’ edge profile requirements.
6.2 Wafer Categories
6.2.1 Particle monitors — Wafers intended for use in evaluating the particulate contamination added by a process
tool must have controlled front and back surface defect properties. Consequently, specifications are provided for
front surface localized light scatterers (LLSs), edge chips, and scratches on both surfaces. If desired, a specification
for back surface LLSs can be negotiated between supplier and purchaser.
6.2.2 Lithography monitors — For development of lithographic and patterning equipment and processes, both
surface flatness and surface defects must be carefully controlled.
6.2.3 Other monitors — This column repeats the basic requirements for developmental wafers. Wafers in this
category are not intended for use in particle counting or litography and patterning. These wafers are suitable for use
in process and inspection equipment development. When used for furnace and thermal processes development wafer
back side, edge surface finish and oxygen content are critical issues in connection with the introduction of slip
during high temperature processing. Bulk iron, oxidation induced stacking faults, and bulk microdefects all can
influence wafer performance in thermal processing and should be controlled for critical tests; appropriate
specification levels should be negotiated between supplier and purchaser.
6.3 Wafer types. As defined in M1 customers may choose one of two different methods of wafer edge profile
specification.
6.3.1 Method A: the edge profile is specified by a set of target parameters and their tolerances (see SEMI M73).
6.3.2 Method B: the edge profile is specified by a target template, drawn from similar profile parameters and a
template width (see SEMI M1 Appendix 3).
Table 1 General Specification for Developmental 450 mm Diameter Polished Single Crystal Silicon Wafers
Wafer Category
Item
2.1
General Characteristics
2.1.1
Growth Method
2.1.3
Crystal Orientation
2.1.4
Conductivity Type
2.1.5
Dopant
2.1.6
FQA radius #1
2.1.8
Wafer surface
declination in respect to
crystal orientation
Particle
Monitors
Lithography
Monitors
Measurement
Other
Monitors
Method
Cz or MCz
(100)
p
B
MF26 (x-ray)
p or n
M1, MF42
B or P
M1, MF1389
223 mm
On-orientation 0.000  1.000
MF26 (x-ray)
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted standard. Permission is granted to
reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other
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5.2.4 Surface defect requirements, including surface metal contamination (see ¶ 6.6.3).
Semiconductor Equipment and Materials International
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Phone:408.943.6900 Fax: 408.943.7943
Wafer Category
Item
Particle
Monitors
2.2
Electrical Characteristics
2.2.1
Resistivity #2
p type wafers
Lithography
Monitors
Measurement
Other
Monitors
Method
M1, MF673
0.5 - 100 Ω·cm
0.005 - 100
Ω·cm
n type wafers
1-20 Ω·cm
Not specified
M1, MF673
2.2.2
Radial Resistivity
Variation (RRG)
- Center to 219 mm from
center.
2.3
Chemical Characteristics
2.3.1
Oxygen Concentration
Not specified
Customer
Specified
M1, MF1188,
MF1366
2.3.2
Radial Oxygen Variation
- Center to 215 mm from
center
Not specified
10%
MF951
2.4
Structural Characteristics
2.4.1
Dislocation Etch Pit
Density
2.4.2
<10%
M1, MF81
 10/cm2
M1, MF1809
Slip
None
MF 1809
2.4.4
Twin Boundary
None
MF1809
2.4.5
Swirl
None
MF1809
2.5
Wafer Preparation Characteristics
2.5.1
Wafer ID Marking#3
SEMI T7
T7
2.5.7
Edge surface conditions
Polished#4
2.5.8
Back surface condition
Polished#4
2.6
Dimensional Characteristics
2.6.1
Diameter
2.6.2
Notch
Depth
Angle
450  0.1 mm
M1, MF2074
dimensions#5
MF1152
1.00+0.25 -0.00 mm
900+50-10
2.6.3
Orientation of Notch axis
<110>  10
2.6.6
Edge profile
See Table 2
2.6.7
Thickness
#2
2.6.8
GBIR, less than
2.6.9
Bow, max
2.6.10
Warp, max
2.6.13
M1, M73
925  25 μm
10 μm
3 μm
MF533
10 μm
MF1530
Customer Specified
MF534
100 μm
50 μm
100 μm
MF1390
Flatness/SFQR
(26x8mm2 site size)
Not specified
42 nm
Not specified
MF1530
2.6.14
Nanotopography
Not specified
Customer
specified
Not specified
M43
2.6.15
Near Edge Geometry
Not specified
Customer
specified
Not specified
M67, M68, M70
2.7
Front Surface Chemistry
Surface Metal
Contamination
2.7.1
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted standard. Permission is granted to
reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other
reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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DRAFT
Document Number: 4624A
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Semiconductor Equipment and Materials International
3081 Zanker Road
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Phone:408.943.6900 Fax: 408.943.7943
Wafer Category
Item
Particle
Monitors
Lithography
Monitors
Measurement
Other
Monitors
Method
2.7.1.1
Sodium
1  1010 per cm2
MF1617
E45
ISO 17331
2.7.1.2
Aluminum
1  1010 per cm2
MF1617
E45
ISO 17331
2.7.1.3
Potassium
1  1010 per cm2
M33
MF1617
E45
ISO 17331
2.7.1.4
Chromium
1  1010 per cm2
M33
MF1617
E45
ISO 17331
2.7.1.5
Iron
1  1010 per cm2
M33
MF1617
E45
ISO 17331
2.7.1.6
Nickel
1  1010 per cm2
M33
MF1617
E45
ISO 17331
2.7.1.7
Copper
1  1010 per cm2
M33
MF1617
E45
ISO 17331
2.7.1.8
Zinc
1  1010 per cm2
M33
MF1617
E45
ISO 17331
2.7.1.9
Calcium
1  1010 per cm2
M33
MF1617
E45
ISO 17331
2.8
Front Surface Inspection Characteristics
2.8.1
Scratches
None
M1, MF523
2.8.3
Pits (COP)
Customer
Specified
Not specified
M1, MF523
2.8.4
Haze
Customer
Specified
Not specified
M1, MF523
2.8.5
Localized Light
Scatterers  0.045 μm
0.16 per cm2
0.32 per cm2
250 per wafer
500 per wafer
M1
(SSIS)
2.8.6
Edge Chips
2.9
Back Surface Inspection Characteristics#6
2.9.1
Edge Chips
None
M1, MF523
None
M1, MF523
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted standard. Permission is granted to
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Document Number: 4624A
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Semiconductor Equipment and Materials International
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Phone:408.943.6900 Fax: 408.943.7943
Wafer Category
Item
Particle
Monitors
Lithography
Monitors
Measurement
Other
Monitors
Method
2.9.9
Scratches - Macro
None
M1, MF523
2.9.10
Scratches - Micro
Customer Specified
M1, MF523
Localized Light
Customer Specified
M1, MF523
Scatterers
#1 This FQA radius results in a nominal edge exclusion of 2 mm; the radius of the wafer is to be center referenced.
#2 Measured at Center Point.
#3 See Related Information 1 for optional alphanumeric marking.
#4 Implies a surface condition and not a particular processing technique.
#5 See Related Information 2 for discussion of inscribed fiducial mark wafer (“notch-free”).
#6 Back surface inspection characteristics are impacted by the type of wafer handling. So far no decision about back surface or
edge handling in the bare wafer manufacturing has been made.
2.9.11
Table 2 Edge Profile Specification for Developmental 450 mm Diameter Polished
Single Crystal Silicon Wafers Edge
Wafer Edge Type Specification
Item
Front edge width
Front bevel angle
Method A
Method B
350  50 μm
350 μm
22.50

22.50
30
Front shoulder radius
202.5  42.5 μm
202.5 μm
Back shoulder radius
202.5  42.5 μm
202.5 μm
Back bevel angle
Back edge width
22.50

22.50
30
350  50 μm
350 μm
30 μm
Template Width
925  25 μm
Thickness#1
Measurement Method
SEMI M73
SEMI M1
Appendix 3
#1 Thickness is not an edge specification but it is listed here for convenience.
6.4 Material and Manufacture — The material shall consist of wafers cut from ingots grown by either the normal
Czochralski or the magnetic Czochralski method, at the supplier’s option.
6.5 Dimensions and Permissible Variations — Wafers shall conform to the dimensions and dimensional tolerances
as specified for the attributes listed in Table 1.
6.5.1 Shape — Although the warp value specified in Table 1 is expected to be adequate for many developmental
purposes, it is now recognized that warp, even with correction for gravitational sag, is not a suitable metric for
specifying wafer shape for all applications. Processing may induce additional warp.
6.5.2 Sori is an attribute that may be specified as agreed between the supplier and the purchaser in lieu of warp. (see
SEMI MF1451)
6.5.3 Bow values will be specified by the customer, depending on his application requirements.
6.5.4 Flatness — GBIR and SFQR are specified in Table 1. NT and ERO values shall meet customer requirements
as specified in the purchase order.
NOTE 1: This is a wafer specification. Equipment specifications may have tighter requirements.
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NOTE 2: Customer preferring wafers without a notch, will have the option to use a fiducial mark inscribed on the wafer backside
as discussed in Related Information 2.
6.5.6 Back Surface Finish — The back surface shall be polished.
6.5.7 Edge Profile — Must be selected as specified in the purchase order. The edge profile shall confirm to one of
two sets of requirements listed in Table 2 at all points on the wafer periphery except the notch region.
6.5.7.1 Edge Surface Finish — The edge surface finish is specified to be “polished,” which is meant to imply a
surface condition and not a particular processing technique.
6.5.8 Fixed Quality Area — The central region of the wafer with a radius of 223 mm is designated as the fixed
quality area (FQA).
NOTE 3: In SEMI M1, the FQA is referenced to the edge of a wafer of nominal diameter by the nominal edge exclusion (see M1,
Fig.1c). For 450 mm wafers, the FQA is being center referenced. The equivalent nominal edge exclusion for the specified FQA
radius is 2 mm. Measurement results acquired with with edge-referenced coordinates must be handled appropriately when
traslating to SEMI M20 coordinate space used in this specification.
NOTE 4: It should also be noted that a larger FQA radius (smaller value of nominal edge exclusion) may be required for circuitquality 450 mm diameter wafers.
6.6 Other requirements
The wafers shall conform to the surface orientation and fiducial axis orientation requirements as specified in Table
1.
NOTE 5: The angular surface orientation tolerance specified in Table 1 is sufficient for wafers intended for general use where
channeling is to be avoided in ion implantation. For applications where maximum channeling along the [100] direction
perpendicular to the (100) wafer surface plane is desired, the surface orientation tolerance must be tightened as discussed in § 7.1
of SEMI M1.
6.6.1 All 450 mm wafers shall be marked with a two-dimensional matrix code symbol on the back surface outside
the fixed quality area as soon after slicing as practical in the manner specified in SEMI T7 in order to provide both
identification of these wafers and traceability of each wafer, going back to the ingot from which it was cut. The
back surface is identified as the wafer surface with the two-dimensional matrix code symbol.
6.6.1.1 Optionally the user may specify an additional alpha-numeric back-surface mark as described in Related
Information 1.
6.6.2 Particulate Contamination (Localized Light Scatterer or LLS) Requirements — Particulate contamination
requirements are specified in Table 1. Particle monitors wafers have tighter requirements than other monitor wafers.
6.6.3 Surface Defect Requirements including surface metal contamination levels, are specified in Table 1.
6.6.4 The wafers shall conform to such other physical characteristics listed in SEMI M1 as may be specified in the
purchase order or contract.
7 Sampling
7.1 Unless other wise specified, ASTM Practice E 122 shall be used to define the sampling plan. When so specified,
appropriate sample sizes shall be selected from each lot in accordance with ANSI/ASQC Z1.4. Each quality
characteristic shall be assigned an acceptable quality level (AQL) or lot tolerance percent defective (LTPD) value in
accordance with ANSI/ASQC Z1.4 definitions for critical, major, and minor classifications. If desired and so
specified in the contract or order, each of these classifications may alternatively be assigned cumulative AQL or
LTPD values. Inspection levels shall be agreed upon between the supplier and the purchaser.
8 Test Methods
8.1 Table 1 of SEMI M1 contains a listing of SEMI, ASTM, DIN, and JEIDA/JIS and ISO test methods that may
apply to the testing of specified attributes of developmental 450 mm diameter silicon wafers.
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted standard. Permission is granted to
reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other
reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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6.5.5 Fiducial Mark — A notch in conformance with the dimensions and tolerances as described in M1 ¶ 6.6.1.
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DRAFT
Document Number: 4624A
Date: 2/13/2016
9.1 Upon request of the purchaser in the contract or order, manufacturer’s or supplier’s certification that the
material was manufactured and tested in accordance with this specification, together with a report of the test results,
shall be furnished at the time of shipment.
9.2 In the interest of controlling inspection costs, the supplier and the purchaser may agree that the material shall
be certified as “capable of meeting” certain requirements. In this context, “capable of meeting” shall signify that the
supplier is not required to perform the appropriate tests as included in the purchase order or contract (see § 8).
However, if the purchaser performs the test and the material fails to meet the requirement, the material may be
subject to rejection.
10 Packing and Package Labeling
10.1 Special packing requirements shall be subject to agreement between the supplier and the purchaser. Otherwise
all wafers shall be handled, inspected, and packed in such a manner as to avoid chipping, scratches, and
contamination and in accordance with the best industry practices to provide ample protection against damage during
shipment.
10.2 Wafers supplied under this specification shall be identified by appropriately labeling the outside of each box or
other container and each subdivision thereof in which it may reasonably expected that the wafers will be stored prior
to further processing. Wafer box labels shall include as a minimum the following information in accordance with
SEMI T3:

Customer Assigned Product Identification Number,

Lot Number,

Vendor Identification Code,

Labeling Date, and

Quantity.
10.3 The lot number shall provide access to information concerning the nominal diameter, conductivity type,
dopant, orientation, resistivity range, and fabrication history of the particular wafers in that lot. Such information
shall be retained on file at the manufacturer’s facility for at least one month after that particular lot has been
accepted by the purchaser, or for a longer time if so specified in the purchase order or contract.
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted standard. Permission is granted to
reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other
reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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9 Certification
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134-2127
Phone:408.943.6900 Fax: 408.943.7943
RELATED INFORMATION 1
ALPHANUMERIC IDENTIFICATION MARK FOR 450 mm
DEVELOPMENTAL WAFER
NOTICE: This related information is not an official part of SEMI Mxx and was derived from the International 450
mm Wafer Task Force. This related information was approved for publication by ballot on [tbd].
R1-1.1 As specified in Table 1 all 450 mm wafers have to be marked with a two-dimensional matrix code symbol
on the back surface as defined by SEMI T7.
R1-1.1.1 However, some customer may require an additional mark, especially during the process development
stages.
R1-1.1.2 This mark contains alphanumeric characters with:

The same message characters as the SEMI T7 mark and appropriate checksum characters as defined by
SEMI M12 and M13 and

Character string as specified in SEMI M12 and M13.
R1-1.1.3 The wafer identification marking positions and dimensions are described in Fig. R1-1
Fiducial Axis
A/N MARK
Edge
Profile
Region
R 223
5
R 225
ction
A/N read dire
1.62  0.03
Edge
Exclusion
Area
All dimensions in
millimeters unless
otherwise indicated
1.40  0.05
Outer
Periphery of
FQA
T7 MARK
from data
223.95  0.15
system
de
co
matrix
t to wafer
in
reference po
center
5.0  0.1 from
Fiducial Axis
Wafer Back Surface
Wafer
Periphery
Notch
8.22  0.05
16.43  0.07
Reference point of
SEMI T7 Mark
Figure R1-1
T7 and Alphanumeric Identification Marking Positions and Dimensions
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted standard. Permission is granted to
reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other
reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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LETTER (YELLOW) BALLOT
DRAFT
Document Number: 4624A
Date: 2/13/2016
DRAFT
Document Number: 4624A
Date: 2/13/2016
RELATED INFORMATION 2
DISCUSSION ON INSCRIBED FIDUCIAL MARK FOR 450 mm
DEVELOPMENTAL WAFER
NOTICE: This related information is not an official part of SEMI Mxx and was derived from the International 450
mm Wafer Task Force. This related information was approved for publication by ballot on [tbd].
NOTICE: This fiducial mark specification option is intended for the customers who choose to use a “notch free”
wafer.
R2-1.1 The wafer notch is used for wafer alignment however it impacts the wafer symmetry and creates a stress
area. Eliminating the notch will improve the wafer symmetry and eliminate the notch related stress but will require
a different alignment method.
R2-1.2 A fiducial mark, inscribed on the back of the wafer has been proposed as an alternative alignment method.
A good mark needs to provide a clear signature, with good angular resolution, provide a robust signature for wafer
theta alignment and be readable through all the process steps.
R2-1.3 The exact dimensions, position and pattern of the fiducial mark have not been defined yet and will have to
be addressed in future working group meetings.
NOTICE: SEMI makes no warranties or representations as to the suitability of the standard(s) set forth herein for
any particular application. The determination of the suitability of the standard(s) is solely the responsibility of the
user. Users are cautioned to refer to manufacturer’s instructions, product labels, product data sheets, and other
relevant literature respecting any materials or equipment mentioned herein. These standards are subject to change
without notice.
By publication of this standard, Semiconductor Equipment and Materials International (SEMI) takes no position
respecting the validity of any patent rights or copyrights asserted in connection with any item mentioned in this
standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and
the risk of infringement of such rights are entirely their own responsibility.
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted standard. Permission is granted to
reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other
reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134-2127
Phone:408.943.6900 Fax: 408.943.7943