Project TE329, existing example No. E-6
Level / Category (ies)
CL 3a, 3b, 3c,
AL 3a, 3b, 3c
Documents (Classification is based on underlined document(s))
GB 2 184 922
DE 3 640 692
FR 2 591 004
JP 62 234 420
Short Version of the Disclosure
A digital phase-locked loop system for providing a digital output signal synchronized with a
stream of data pulses, comprising:
- variable oscillator means for generating a digital output signal comprises of alternating
high and low level pulse windows in which each window is comprised of a plurality of
successive segments of equal duration, wherein the oscillator means is alterable to control the
number of segments in each window in a sequence of windows to provide one of a plurality of
predetermined set output frequencies;
- phase detection means for determining the position of each data pulse relative to the
segments of a window in which it occurs; and
- processing means, responsive to the phase detection means, for controlling the oscillator
means to (a) alter the set output frequency as a function of the positions of a minimum of
three consecutive data pulses with respect to the segments of the windows in which they occur
and (b) alter the number of segments in an individual window as a function of the position of
a data pulse with respect to the segments of said individual window and as a function of the
positions of a minimum of two data pulses with respect to the segments of windows in which
they occur.
Representative Prior Art
Digital phase-locked loop system including a variable multiple state component such as a
counter or shift register driven by a sample clock. The carry output of the shift register
provides an output signal of variable frequency which is used to toggle the recovered clock
window signal. The output frequency of the shift register is varied by adding or subtracting
states. In order to reduce the frequency of the window signal, one state is added, and in order
to increase the frequency of the window signal, one state is subtracted.
A phase detector is implemented with a microprocessor or logic array and determines when
the transition pulses arrive with respect to the states of the shift register. The logic array
incorporates an algorithm to determine frequency corrections as a function of the
determination of the state of occurrence of the transition pulses. If a transition pulse does not
arrive in the correct state, the phase detector provides an error signal to alter the number of
states, and thus the output frequency, of the shift register.
Invention Information
I1.
A digital phase-locked loop system in which phase detection and error amplification is
provided by programmed state machines which drive a digital controlled oscillator including
a variable state shift register to change the frequency of the shift register output if
appropriate. Filter operation is provided by latching state machine output terms and feeding
them back at later clock times.
The oscillator means is controlled in order to (a) alter the set output frequency as a function
of the positions of a minimum of three consecutive data pulses with respect to the segments of
the windows in which they occur and (b) alter the number of segments in an individual
window as a function of the position of a data pulse with respect to the segments of said
individual window and as a function of the positions of a minimum of two data pulses with
respect to the segments of windows in which they occur.
Additional Information
A1.
Apparatus for reading digital data from a disk storage, where clock information has been
embedded in the data information (see "Field of the invention", from second paragraph until
end of section).
A2.
Clock recovery for data synchronisation in digital data transmission (see "Field of the
invention", first paragraph).
Motivation
Even though the invention is directed to a device per se, the main applications that are
explicitly mentioned appear to deserve a classification, also according to § 85(c)(d) and §
90(c) of the Guide to the eight edition of the IPC.
Identification of Potential Subclasses
Subject Matter
Tool
Query
IPC Places
I1
Catchword index
Phase-locked loop
H03L 7/00
A1
Catchword index
Storage of information
G11B
A2
Catchword index
Communication or Transmission
H04
Analysis and Selection of Classification Symbols
Core Level
The main invention relates to a (digital) phase-locked loop. For such technical term, the
catchword index provides a precise main group:
H03L 7/00 " Automatic control of frequency or phase; Synchronisation".
Under this main group, we find:
7/06 . using a reference signal applied to a frequency- or phase-locked loop
7/08 . . Details of the phase-locked loop
This group seems then the most suitable for classifying I1.
Additional information:
A1
An application specifically mentioned in the document (see "Field of the invention") is the
use of the invention in the decoding of information encoded on a disk using modified
frequency modulation (MFM) format.
Storage of information based on relative movement between record carrier and transducer,
e.g. disks, is covered by G11B.
Main group G11B 20/00 covers "Signal processing not specific to the method of recording or
reproducing; Circuits therefor "
20/10 .
Digital recording or reproducing
20/14 . . using self-clocking codes
The latter appears to be the best fitting group.
A2
The reference in group H03L 7/00 indicates that "synchronising in digital communication
systems, see the relevant groups in class H04".
Digital communication systems are mentioned in the introduction to the disclosure.
Under H04, the most appropriate subclass for the case at hand appears to be
H04L Transmission of digital information
under which the following groups seem relevant:
7/00
Arrangements for synchronising receiver with transmitter
7/02 .
Speed or phase control by the received code signals, the signals containing no
special synchronisation information
7/033 . . using the transitions of the received signal to control the phase of the synchronisingsignal- generating means, e.g. using a phase-locked loop
Modified frequency modulation coding of data is mentioned in the description. Such coding
technique per se is covered by group H03M 5/00, but the document does not disclose MFM in
such details as to deserve a class.
Advanced Level
The main invention relates to a (digital) phase-locked loop. For such technical term, the
catchword index provides a precise main group:
H03L 7/00 " Automatic control of frequency or phase; Synchronisation".
Under this main group, we find:
7/06 . using a reference signal applied to a frequency- or phase-locked loop
7/08 . . Details of the phase-locked loop
7/085 . . . concerning mainly the frequency- or phase-detection arrangement including the
filtering or amplification of its output signal
This group seems the most suitable for classifying the aspects of phase error amplification and
filter operation (see fig. 9, blocks 58, 64, 66) characterising I1.
On the other hand, the details of I1 concerning the control of the oscillator (see fig. 9, blocks
60, 60a) falls within the scope of group:
7/099 . . . concerning mainly the controlled oscillator of the loop
Additional information:
A1
An application specifically mentioned in the document (see "Field of the invention") is the
use of the invention in the decoding of information encoded on a disk using modified
frequency modulation (MFM) format.
Storage of information based on relative movement between record carrier and transducer,
e.g. disks, is covered by G11B.
Main group G11B 20/00 covers "Signal processing not specific to the method of recording or
reproducing; Circuits therefor "
20/10 .
Digital recording or reproducing
20/14 . . using self-clocking codes
The latter appears to be the best fitting group.
A2
The reference in group H03L 7/00 indicates that "synchronising in digital communication
systems, see the relevant groups in class H04".
Digital communication systems are mentioned in the introduction to the disclosure.
Under H04, the most appropriate subclass for the case at hand appears to be
H04L Transmission of digital information
under which the following groups seem relevant:
7/00
Arrangements for synchronising receiver with transmitter
7/02 .
Speed or phase control by the received code signals, the signals containing no
special synchronisation information
7/033 . . using the transitions of the received signal to control the phase of the synchronisingsignal- generating means, e.g. using a phase-locked loop
Modified frequency modulation coding of data is mentioned in the description. Such coding
technique per se is covered by group H03M 5/00, but the document does not disclose MFM in
such details as to deserve a class.
Subject
Matter
Analysis of Subclass
Selection
Subclass
I1
Title covers subject
matter
H03L
A1
Title covers subject
matter
G11B
A2
Reference in H03L 7/00
H04L
Analysis of Group
Selection
IPC CL
IPC AL
IPC(2006)
H03L 7/085
H03L 7/085
H03L 7/099
H03L 7/099
Common rule
G11B 20/14
G11B 20/14
Common rule
H04L 7/033
H04L 7/033
Common rule
Complete Classification
The complete core and advanced level classification for this document based on the above
analysis is as follows:
Core level
Int. Cl. (2006)
H03L7/08
G11B20/14
H04L7/033
Advanced level
Int. Cl.
H03L7/085
H03L7/099
G11B20/14
H04L7/033