Test 1
ECE 484/584 -- Spring 2005
Chapters 1 - 4.5
Name: ___________________________
Student Number: ______________________
1) Given 4 bits to represent data in memory, what is the range of signed integers that can be represented if
two’s complement representation is used? (5 points) Also, what is the binary representation for -9? (5
points)
range: (-8) – 7
-9 can’t be represented using only 4 bits and using 2’s complement representation
2) Given 4 bits to represent data in memory, what is the range of signed integers that can be represented if
sign-and-magnitude representation is used? (5 points) Also, what is the binary representation for -1? (5
points)
range: (-7) – 7
-1 = 1001
3) Give the 8-bit representation of the numbers -10 and 100 in sign-and-magnitude and two’s complement
representations and show how each representation is sign-extended to 16 bits. (10 points)
sign-and-magnitude (-10): 1000 1010
two’s complement (-10): 1111 0110
sign extended:
sign extended:
1000 0000 0000 1010
1111 1111 1111 0110
sign-and-magnitude (100): 0110 0100
two’s complement (100): 0110 0100
sign extended:
sign extended:
0000 0000 0110 0100
0000 0000 0110 0100
4) Given that a program executes on computer A in 7 seconds. This particular program performs both
floating point and integer operations. The floating point operations make up 40% of the total execution
time of the program on machine A. Machine B incorporates new floating point hardware that can improve
the time for floating point operations. By what amount does machine B need to improve the floating point
operations of machine A in order to achieve a new execution time of 5 seconds? (10 points)
 execution _ time _ affected _ by _ imp. 
  exe _ time _ unaffected
execution _ time _ after _ improvement  
Speedup


2.8
5
 4.2 sec
Speedup
2.8
0.8 
speedup
2.8
speedup 
 3.5
0.8
5) Draw a 1-bit ALU capable of performing or supporting the instructions AND, OR, ADD, SUB, SLT.
Show all data and control lines. (10 points) Then, draw a 4-bit ALU using an abstraction for the 1-bit
device you designed in part one of this question. Again, show all data and control lines. (10 points)
Finally, complete a table showing all the values for the control signals needed to implement each of the
instructions. (5 points)
6) Translate the following MIPS assembly language into machine code. The address of each instruction is
given on the left in decimal. All machine language must be in binary. (15 points)
3004
3008
3012
3016
3020
3024
label:
exit:
in binary:
3004 000000
3008 000100
slt
beq
addi
j
addi
…
$s0, $s1, $s2
$s0, $zero, label
$s1, $s1, 1
exit
$s2, $s2, 1
10001
10000
10010
00000
10000
00000
0000 0000 0000 0010
101010
3020 – 3012 = 8 bytes  8/4 = 2 words
3012
3016
001000
000010
10001 10001 0000 0000 0000 0001
00 0000 0000 0000 0010 1111 0100
3024/4 = 756
3020
3024
001000
10010
10010
0000 0000 0000 0001
in hex:
02 32 80 2a
12 00 00 02
22 31 00 01
08 00 02 f4
22 52 00 01
7) Now assume we add a second program to our workload, Program B, such that the total workload is
composed of 50% Program A and 50% Program B. The following table shows the execution times of
Program A and B on each machine. Which machine is faster and by how much? (10 points)
Program A
Program B
Machine 1
5
6
Total execution time:
11
Machine 2
10
5
15
perf _ 1 exe _ time _ 2 15


 1.36
perf _ 2 exe _ time _ 1 11
OR
Average execution time: 5.5
perf _ 1 7.5

 1.36
perf _ 2 5.5
So, machine 1 is 1.36 times faster than machine 2.
7.5
8) Reverse engineer the MIPS assembly code from the following machine code given in hexadecimal. (5
points)
01 0C 80 24
000000
01000
and
01100
10000 00000 100000
$s0, $t0, $t4
9) Given the following C code and the assumptions, write the MIPS assembly for the calling function and
the subroutine. Assume that variable a is allocated to register $s1, variable b is allocated to register $s2,
variable c is allocated to register $s3, variable max is allocated to register $s4, variable m is allocated to
register $s1, all input and output parameters are allocated according to the conventions used in MIPS
assembly, and finally that any temporary registers needed will be allocated to a temporary register ($t0 $t9). Preserve only those registers that must be preserved across the subroutine call. The MIPS assembly
must be CORRECT assembly language instructions. NO Pseudo-instructions are allowed. (20 points)
int
maximum (int x, int y, int z) {
int m;
if ((x >= y) && (x >= z))
m = x;
else if ((y >= x) && (y >= z))
m = y;
else if ((z >= x) && (z >= y))
m = z;
return (m);
}
void
main (void) {
int a, b, c, max;
…
max = maximum(a, b, c)
…
}
main:
add
add
add
jal
add
j
$a0, $zero, $s1
$a1, $zero, $s2
$a2, $zero, $s3
maximum
$s4, $zero, $v0
done
maximum:
addi
sw
$sp, $sp, -4
$s1, 0($sp)
slt
slt
or
beq
$t0, $a0, $a1
$t1, $a0, $a2
$t2, $t0, $t1
$t2, $zero, returnx
slt
$t0, $a1, $a0
slt
or
beq
$t1, $a1, $a2
$t2, $t0, $t1
$t2, $zero, returny
slt
slt
or
beq
$t0, $a2, $a0
$t1, $a2, $a1
$t2, $t0, $t1
$t2, $zero, returnz
returnx: add
$v0, $a0, $zero
j
exit
returny: add
$v0, $a1, $zero
j
exit
returnz: add
$v0, $a2, $zero
j
exit
exit:
lw
addi
jr
done:
$s1, 0($sp)
$sp, $sp, 4
$ra
10) List the four (4) fundamental principles of design and give two (2) examples of how each is used in the
design of the MIPS architecture and MIPS assembly language (20 points – 1 point for the principle and 2
points for each example)
EXTRA CREDIT: Provide additional examples of each design principle for 2 points of extra credit
per example.
A. Simplicity favors regularity:
1) All arithmetic instructions use 3 operands.
2) All MIPS instructions are 32-bits in length.
B. Smaller is faster:
1) Limiting # of registers
2) Using the RISC theory
C. Good designs require good compromises:
1) Introduction of I format
2) Introduction of J format
3) Efforts to balance performance and costs
D. Make the common case fast:
1) Introduction of immediate addressing
2) Using RISC theory
11) Identify which addressing mode is used by each of the following instructions, and describe how the
addressing mode creates the address of the operand(s). (4 points each)
a) j label
Pseudodirect addressing; 26 bits of immediate data in instructions is concatenated with top 4 bits of PC to
create jump destination (word relative)
b) ori $s0, $s1, 4
Immediate addressing; operand is in the instruction itself
c) lw $s0, 0 ($s1)
Base/displacement addressing; contents of base register ($s1) are added to immediate data in the instruction
to get address of operand
d) bne $t0, $t1, label
PC-relative addressing; PC + 4 is added to immediate data in instructions to create address for branch
(word relative)