Fred E. Wahl
Milpitas, CA
O: (408) 262-0471, C: (408) 504-8035
fred@fred-wahl.net Resume web page: www.fred-wahl.net
OBJECTIVEs
Engineer OR Supervisor in areas of Device Engineering, IC Design Support, Semiconductor Modeling and
Characterization, IC Design (entry-level), CAD tool development, Yield Engineering, OR Failure Analysis.
SUMMARY
Educated through MSEE level with more than 15 years of Semiconductor experience and related hardware,
software and systems use and development. Work history in assisting IC Physical Design, Technology
Qualification, Characterization Tool use and development, Spice Modeling and tool development, Process
Control Database system development and use. Assisted qualification of several cycles of CMOS process
technology and related preparations for IC design. Assisted new circuit debug and yield improvements and
contributed to finding IC manufacturing cost savings. Supervised / Instructed many new-grad / H1B engineers.
TECHNICAL SKILLS
Scientific / Engineering:
Physics, Math, Statistics and EE training. Semiconductor device physics and
parameters, Device measurements, Test chip design and layout. Electronics testing,
Circuit simulation, some CAD and TCAD tools, Test hardware acquisition, system
integration, programming and use. Tools: Ledit, Pdracula, BSIMpro, BSIM-ET,
Hspice, Smartspice, Arcadia, Mathlab, Cornerstone, IBASIC, HPVEE, LabView,
IVEX Winboard, VERILOG
Informational:
Use of web-based information systems, Design of relational and web-based
databases, Web page design. Tools: Informix, SQL, Erwin, Sybase PowerBuilder,
Cute FTP, Dreamweaver, IEEE Xplore, Copernic Agent Pro, PayPal buttons
Computers / Programming: Sun/PC hardware and software, Ethernet, Backups, Unix, Linux, Microsoft
Windows. Languages: BASIC, Visual Basic, C, C++, shell script, PERL, Latex,
Emacs, Assembly
Office Tools:
Adobe Acrobat, Distiller, Photoshop, Excel, Word, PowerPoint, Project
EXPERIENCE
CIRRUS LOGIC INC, Fremont CA
1991- March 2003
Manager, Technology Characterization (2001-March 2003)
Maintained Technology Characterization service as group function transferred to new corporate headquarters in
Austin, Texas. Assisted transfer and training of Texas personnel.
 Developed an economical characterization system using Agilent/HP E5250A, HP4156B and HP4284A
 Coordinated test chip testing and modeling project at CSM Foundry onsite in Singapore
 Insured success of new Yield Improvement web-based database by feeding it data from old database
Manager Characterization, Design Infrastructure (1999-2001)
Assisted group project to create web-page “back end”, “physical” design and “process” information system also
known as “Design Kit”. Supported Design, Product, and Fab engineering requested Yield Improvements and
characterizations. Provided maintenance of Process Parameter Yield Improvement client-server database.
 Wrote Spice Modeling Specification to help guarantee ‘first time success’ designs
 Assisted content choice and testing of Unix automated Foundry Spice Model QA method
Manager, Characterization and Modeling (1998-1999)
Provided Spice Model Development and Quality Assurance. Used BSIMpro and BSIM-ET to develop corporate
BSIM 3v3 Spice Models. Capacitance-voltage measurements used to create model capacitance parameters.
Calibrated models to silicon using Ring Oscillator simulations and measured gate delays.
 Model accuracy improved using back-annotated netlist interconnect parasitics calculation
 Promoted database use resulting in Yield Improvement for users at Fremont, Austin and Colorado sites
(end page 1 of 2)
Fred E. Wahl
C: (408) 504-8035
fred@fred-wahl.net
Page 2 of 2
(CIRRUS LOGIC, continued)
Section Manager, Characterization (1994-1998)
Manage and train Characterization section reporting to Director of Technology Qualification. Projects: Electrical
Design Rules development and test, Test chip design and layout, Parametric testing, Characterization,
Interconnect parasitics tool evaluation, TLP snapback test, and Wafer Level Reliability methods development.
 Specified second HP4062 and brought it up for advanced Technology Characterization testing
 Led project to develop Engineering client-server database using Informix and PowerBuilder
 Developed Pelgrom field-effect transistor mismatching methodology; results used by design
Engineer, Etest and Characterization (1992-1994)
Created Characterization Lab and acquired needed test equipment. Developed Process and Device
Characterization/Technology Analysis Reports. Performed wafer split lot analysis for Yield Improvement.
Led system requirements definition and prototyped engineering databases for Yield Monitoring.
 Produced, edited Training Videos for Etest operators and technicians consistent with specs
 Wrote Etest specifications for operations, test maintenance and engineering
 Designed and contracted building of an Electromagnetic shield box for lab prober
Senior Device Engineer (1991-1992)
Set up corporate Etest/Process Control Monitor capability using HP4062 test system and Electroglas automatic
wafer prober. Provided Device measurements to support yield improvement. Standardized parameters and test
definitions. Developed lot parameter Pass/Fail reports for wafer lot acceptance (WAT).
 Developed a test system software design which served the company for the next 10 years
TECHNOLOGY MODELING ASSOCIATES, Palo Alto CA
1990-1990
Senior Member, Technical Staff
Continued Development of Unix Spice Modeling software TOPEX. Assisted attempts to migrate TOPEX to PC
 Produced one full new release and one beta release and several application notes
 Presented slide show on BSIM in TOPEX at TMA Santa Clara TechMart annual customer meeting
OTHER RELATED EMPLOYMENT
SIGNETICS/PRLS (Philips Research Labs Sunnyvale), Sunnyvale CA . Developed Wafer Contour Mapping
System to study process uniformity. BiCMOS process development team member. Spice/SLIC Modeling.
Bipolar Memory Yield Engineering. Wafer Sort Engineering. Ion Implant process qualification. 10-bit D/A
development. Spreading Resistance doping profile characterization. Implant and thin film QA tool design.
EDUCATION
MSEE, University of Santa Clara, Santa Clara, CA. Semiconductor Emphasis with analog and digital design
BS Physics / Applied Math, San Jose State University, San Jose, CA
Completed all technical coursework for AS Electronics, Foothill Community College, Los Altos CA.
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PROFESSIONAL DEVELOPMENT
Digital Design using VERILOG, UCSC ext instructor Charles Dancak (2004 )
CMOS Analog Integrated Circuits, Georgia Tech instructor Dr. Phillip E. Allen (2004 )
Developing Engr Appl with MS Visual C++ Devel Studio, instructor Dr. James W. McDonald. (2004 )
Intro to VLSI and ASIC Design, UCSC ext instructors Mukesh Amlani and Suresh Honnenahalli (2004 )
FSA sponsored Spice and Interconnect Modeling Workshops (2002 and 2000)
High Speed Circuit Design for Digital Designers, Cirrus, instructor Howard Johnson (1999)
Using BSIMpro to extract BSIM CMOS parameters, BTA, instructor Gang Zhang (1999)
MOS Devices: Physics, Technology, Reliability, Modeling and Characterization, UC Berkeley Extension
- instructors Chenming Hu and Ping Ko (1998)
Semiconductor Process and Device Characterization, Arizona State Univ instructor Dieter Schroder (1997)
Relational Database Design, Structured Query Language (SQL), etc., Informix (1994)
Design for Manufacturability, Cirrus, instructor Richard Post (1993)