<< note: interaction with AHCI spec requirements & 'shadow status register' >>
- - will Mark Overby ever do anything with HBA-2 ?
====================================
references:
Serial ATA Advanced Host Controller Interface (AHCI) 1.3
Serial ATA International Organization: Serial ATA Revision 3.0
====================================
From 7.55.2 SLEEP Description, this text should be in AST:
This command shall cause the device to set the BSY bit to one, prepare to enter Sleep mode,
clear the BSY bit to zero and assert INTRQ.
The host shall read the Status register in order to clear the Interrupt Pending and allow the device
to enter Sleep mode. Because some host systems may not read the Status register and clear the
Interrupt Pending, a device may release INTRQ and enter Sleep mode after a vendor specific
time period of not less than 2 s.
SATA: HBA manages BSY. device does not know when host reads HBA
SATA: HBA and device manages INTRQ, not the device
SATA: enter Sleep mode after a vendor specific time period of not less than 2 s
In Sleep mode, the device shall only respond to the assertion of the RESET- signal and the
writing of the SRST bit in the Device Control register and shall release the device driven signal
lines (See Figure 4).
SATA: COMRESET (or) receiving Register Host to Device FIS with Control bit =0 and
SRST=0->1
AHCI: does not address this
SATA: 11.3 Software reset protocol
When the host sends a Register FIS with a one in the SRST bit position of the Device Control
register byte, regardless of the device power management mode (e.g. SLEEP, STANDBY), the
device shall execute the software reset protocol.
The host shall not attempt to access the Command Block registers while the device is in Sleep
mode.
The only way to recover from Sleep mode is with a software reset, a hardware reset, or a
DEVICE RESET command.]
===================================
this text should be in AST
In 4.18: The deleted material needs to appear in the parallel transport: “To perform a bus
release the device shall clear both DRQ and BSY to zero. When selecting the other device
during overlapped operations, the host shall disable assertion of INTRQ via the nIEN bit on
the currently selected device before writing the
to select the other device and then may re-enable interrupts.”
===================================
The following statements needs to appear in AST: “Following an interface CRC error on a
the data payload, if the device transmits a response that updates the Status Register it
may set bit 7 (i.e. the ICRC bit) to one in the Error field”
SATA:
10.3.2 CRC Errors on Data FISes
Following a Serial ATA CRC error on a Data FIS, if the device transmits a Device-to-Host FIS it
shall set the ERR bit to one and both the BSY bit and DRQ bit cleared to zero in the Status field,
and the ABRT bit set to one in the Error field. It is recommended for the device to also set the bit
7 (i.e. ICRC bit) to one in the Error field. See ATA8-ACS.
There is no Device-to-Host FIS transmitted after a Serial ATA CRC error on the last Data FIS of a
PIO-in command nor following a Serial ATA CRC error on the ATAPI command packet transfer.
Thus, there is no mechanism for the device to indicate a Serial ATA CRC error to the host in
either of these cases. The host should check the SError register to determine if a Link layer error
has occurred in both of these cases.
========================================================
Command Completion (4.17.4.3)
- See SDB FIS
4.1.17 command aborted
Command aborted is command completion with ABRT bit set to one in the Error register, and
ERR bit set to one in the Status register.
4.1.18 command completion
Command completion describes the completion of an action requested by command, applicable
to the device. Command completion also applies to the case where the command has
terminated with an error, and the following actions occurred:
a) the appropriate bits of the Status Register have been updated
b) BSY & DRQ bits have been cleared to zero
c) assertion of INTRQ (if nIEN is active-low), assuming that the command
protocol specifies INTRQ to be asserted
In Serial ATA, the register contents are transferred to the host using a Register - Device-to-Host
FIS.
========================================================
Busy bit (6.2.3)
- Status field bit 7 in Register Device to Host FIS "BSY"
- Status field bit 7 in PIO Setup FIS
- E_Status field bit 7 in PIO Setup FIS
- is not transported in the Set Device Bits FIS
Normal Output Status field bit 7 (7.1.5) "BSY"
- Device field bit 7 in Register Device to Host FIS
- Device field bit 7 in PIO Setup FIS
- E_Status field bit 7 in PIO Setup FIS
- is not transported in the Set Device Bits FIS
<< note: interaction with AHCI spec requirements & 'shadow status register' >>
host sees BSY via host adapter
host adapter is updated by sending and receiving FISes
BSY is set to one to indicate that the device is busy. After the host has written the Command
register the device shall have either the BSY bit set to one, or the DRQ bit set to one, until
command completion or the device has performed a bus release for an overlapped command.
The BSY bit shall be set to one by the device only when one of the following events occurs:
1) after either the negation of RESET- or the setting of the SRST bit to one in the Device
Control register;
2) after writing the Command register if the DRQ bit is not set to one;
3) between blocks of a data transfer during PIO data-in commands before the DRQ bit is
cleared to zero;
4) after the transfer of a data block during PIO data-out commands before the DRQ bit is
cleared to zero;
5) during the data transfer of DMA commands either the BSY bit, the DRQ bit, or both shall
be set to one;
6) after the command packet is received during the execution of a PACKET command.
NOTE The BSY bit may be set to one and then cleared to zero so quickly, that host
detection of the BSY bit being set to one is not certain.
When BSY is set to one, the device has control of the Command Block Registers and:
1) a write to a Command Block register by the host shall cause indeterminate behavior
except for writing DEVICE RESET command;
2) a read from a Command Block register by the host may yield invalid contents except for
the BSY bit itself.
The BSY bit shall be cleared to zero by the device:
1) after setting DRQ to one to indicate the device is ready to transfer data;
2) at command completion;
3) upon releasing the bus for an overlapped command;
4) when the device is ready to accept commands that do not require DRDY during a poweron,
hardware or software reset.
When BSY is cleared to zero, the host has control of the Command Block registers, the device
shall:
1) not set DRQ to one;
2) not change ERR bit;
3) not change the content of any other Command Block register;
4) set the SERVbit to one when ready to continue an overlapped command that has been
bus released.
5) clear the DSC bit to zero when an action that uses this bit is completed.
=========================
Device Ready Bit (6.2.8)
- Status field bit 6 in Register Device to Host FIS
- Status field bit 6 in PIO Setup FIS
- E_Status field bit 6 in PIO Setup FIS
- Status Hi field bit 2 in Set Device Bits FIS
"DRDY"
<< note: interaction with AHCI spec requirements & 'shadow status register' >>
host sees BSY via host adapter
host adapter is updated by sending and receiving FISes
------------SATA rev. 3.0 only mentions DRDY for
- read fpdma queued
- write fpdma queued
- ncq queue management
- SEMB
- port multiplier
--------The DRDY bit shall be cleared to zero by the device:
1) when power-on, hardware, or software reset or DEVICE RESET or EXECUTE DEVICE
DIAGNOSTIC commands for devices implementing the PACKET command feature set.
When the DRDY bit is cleared to zero, the device shall accept and attempt to execute commands
as described in clause 8.
The DRDY bit shall be set to one by the device:
1) when the device is capable of accepting all commands for devices not implementing the
PACKET command feature set;
2) prior to command completion except the DEVICE RESET or EXECUTE DEVICE
DIAGNOSTIC command for devices implementing the PACKET feature set.
When the DRDY bit is set to one:
1) the device shall accept and attempt to execute all implemented commands;
2) devices that implement the Power Management feature set shall maintain the DRDY bit
set to one when they are in the Idle or Standby modes.
<< note: interaction with AHCI spec requirements & 'shadow status register' >>
host sees DRQ via host adapter
host adapter is updated by sending and receiving FISes
Data Request bit (6.2.5)
- Status field bit 3 in Register Device to Host FIS
- Status field bit 3 in PIO Setup FIS
- E_Status field bit 3 in PIO Setup FIS
- is not transported in the Set Device Bits FIS
"DRQ"
DRQ indicates that the device is ready to transfer data between the host and the device.
After the host has written the Command register the device shall either set the BSY bit to one or
the DRQ bit to one, until command completion or the device has performed a bus release for an
overlapped command.
The DRQ bit shall be set to one by the device:
1) when BSY is set to one and data is ready for PIO transfer;
2) during the data transfer of DMA commands either the BSY bit, the DRQ bit, or both shall
be set to one.
When the DRQ bit is set to one, the host may:
1) transfer data via PIO mode;
2) transfer data via DMA mode if DMARQ and DMACK- are asserted.
The DRQ bit shall be cleared to zero by the device:
1) when the last word of the data transfer occurs;
2) when the last word of the command packet transfer occurs for a PACKET command.
When the DRQ bit is cleared to zero, the host may:
1) transfer data via DMA mode if DMARQ and DMACK- are asserted and BSY is set to one.
========================================================
Normal Output Device field bit 6 (7.1.5)
"command dependent"
- Device field bit 6 in Register Device to Host FIS
- Device field bit 6 in PIO Setup FIS
Normal Output Device field bit 4 (7.1.5)
"DEV"
- Device field bit 4 in Register Device to Host FIS
- Device field bit 4 in PIO Setup FIS
Bit 4, DEV, in this register selects the device. Other bits in this register are command dependent
(see clause 8).
SATA:
DEV bit in the Device register / Device shadow register / shadow Device register
13.1 Parallel ATA Emulation
Emulation of parallel ATA device behavior as perceived by the host BIOS or software driver, is a
cooperative effort between the device and the Serial ATA host adapter hardware. The behavior of
Command and Control Block registers, PIO and DMA data transfers, resets, and interrupts are all
emulated.
The host adapter contains a set of registers that shadow the contents of the traditional device
registers, referred to as the Shadow Register Block. All Serial ATA devices behave like Device 0
devices. Devices shall ignore the DEV bit in the Device field of received Register – Host to Device
FISes, and it is the responsibility of the host adapter to gate transmission of Register – Host to
Device FISes to devices, as appropriate, based on the value of the DEV bit.
Error Output Status field bit 7 (7.1.5) "BSY"
- Status field bit 7 in Register Device to Host FIS
- Status field bit 7 in PIO Setup FIS
- E_Status field bit 7 in PIO Setup FIS
<< note: interaction with AHCI spec requirements & 'shadow status register' >>
host sees BSY via host adapter
host adapter is updated by sending and receiving FISes
========================================================
Error Output Device field bit 6 (7.1.5) "command dependent"
- Device field bit 6 in Register Device to Host FIS
- Device field bit 6 in PIO Setup FIS
Error Output Device field bit 4 (7.1.5)
"DEV"
- Device field bit 4 in Register Device to Host FIS
- Device field bit 4 in PIO Setup FIS
Bit 4, DEV, in this register selects the device. Other bits in this register are command dependent
(see clause 8).
Error Output Device field bit 3 (7.1.6)
"command dependent"
- Device field bit 3 in Register Device to Host FIS
- Device field bit 3 in PIO Setup FIS
Device Signatures for Normal Outputs
========================================================
NCQ Normal Output SATA Status (Table 116)
========================================================
NCQ Read Command Aborted Output SATA Status (Table 156)
========================================================