Http://www.eej.ulst.ac.uk/~ian/modules/EEE515J1_TUT.doc
IMcC 30-11-04
A Selection of tutorials listed in Lectures
Lecture 4, slide #12
(a)
Design a counter that counts from 0 to 15 but misses out 13 (a superstitious counter)
(b)
Design an excess-3 counter that counts from binary 0011 to 1100 by
(b)(i) Designing a counter that uses the desired outputs as the actual state codes.
(b)(ii) Designing an output combinational circuit that has a 4 bit BCD input and a 4 bit
Excess-3 output
(c) Design an Up/Down Counter that counts 0 to 7, the circuit has one input labeled DIRN.
Lecture 5, slide #5
L5(a) develop circuits to o/p 3 pulses
L5(b) develop circuits to o/p 5 pulses
Lecture “ex3.doc” page 1
A
0/
0
1/
0
B
X/0
C
X/1
TUT3-Q2
TUT3-Q3
TUT3-Q4
TUT3-Q5
Reimplement using Two T-types and a state code A=00,B=11,C=01
Reimplement using Two JK-types and a state code A=00,B=10,C=11
Reimplement using Two D-types and a state code A=00,B=01,C=10
Reimplement using Two D-types and a state code A=001,B=010,C=100
Lecture “Lab3.doc” page 1
Exercise: 3(a) Design a fully synchronous 3 bit counter that counts from 0 to 5, add a
combinational circuit to its output that detects 101. (use the full state table method).
Exercise 3(b) Design a 4 bit counter that counts from 0 to 9, using D-types. You can use the
equations from the file egbcdcnt.pdf on the website, or design your own. Modify or add a
count enable function, either by inserting 2 way mux (switches) or by inspecting the equations
and adding the control input or by designing the counter form scratch. Add a RCO output as
well, this counter will have a CLOCK and CNT_EN inputs ( and possibly reset) and have
Q[3..0] outputs and a RCO output ( that detects 1001 or 9).
Http://www.eej.ulst.ac.uk/~ian/modules/EEE515J1_TUT.doc
IMcC 30-11-04
ASMtuts.doc (selected questions)
Produce an English description of a solution to the problems below; Give an ASM chart and a
block diagram of a suitable Data Processor, Identify the Control Unit of your solution and list
design equations that would allow it to be implemented in a simple large PAL. Use One-Hot
encoding.
As revision of FSM design, re-design the Control Logic by presenting a conventional State
Diagram. From this state diagram check that the number of states is minimal (ie. Perform
state reduction) and implement the FSM using a "good" binary assignment (i.e apply the YWigwam rules or a grey code) and D-Type flipflops. Repeat the implementation using JK
and/or Flipflops.
QAsm2
Count the number of double zeroes in a 32 bit word; x000x gives an o/p of 2
QAsm3
An 8 bit A/D has an SC input and an EOC output to Start a conversion and
indicate when the End of conversion occurs. Design a RS232 transmitter, 8 bits
no parity 2 stop bits ( this is a bit long for an exam question…)
QAsm9
y(t)=x(t)/z(t) hint use successive subtraction
From ASICtut1.doc
QAT1 For a simple hypothetical CPU present the following;
(a) Sketches of how improvements can be made.
(b) List of available addressing modes that can be executed.
(d) English description and detailed Fetch-Execute tables for the following instructions
(i)LD #nn
Load immediate
(ii)ADD nn
Add direct
QAT2
(a) Sketch a circuit for the simplest viable Control Unit using Microcoding and cost it in
terms of bits
(b) Sketch modifications to the basic architecture and calculate the savings.
(c) Give microcode for each of the instructions above.
(I) LD #nn
Load immediate
(ii) ADD nn Add direct
QAT6 Given a CPU such as SHC01 calculate roughly how many flipflops it contains;
(a) Sketch a suitable SCANPATH cell that could replace each flipflop.
(b) Sketch how it might be interconnected inside the CPU.
(c) Descibe with examples how testing might be undertaken.
(d) Calculate the cost of test if a tester with a 100 Mhz Clock is available. Show ALL your
working and assumptions