Author:
Version:
Date:
Hardware Design:
 
BLN
Technical Laboratory Automation Group
Jeroen Franken
0.5
10 th April, 2008
J.C.L. van de Griendt
G.A. Harkema
F.C. van Nijmweegen


1 Introduction ......................................................................................... 3
2 The ADC subfunction ............................................................................... 4
2.1
ADC Hardware features ..................................................................... 4
2.1.1
Analog input specifications ............................................................. 4
2.1.2
Gain ......................................................................................... 5
2.1.3
Input filter (optional) .................................................................... 5
2.2
ADC Memory Modes .......................................................................... 5
2.2.1
Memory Mode 0: Memory disabled ..................................................... 6
2.2.2
Memory Mode 1: Single sweep mode .................................................. 6
2.2.3
Memory Mode 2: Continuous mode .................................................... 6
2.3
Available Sample Rates ..................................................................... 7
2.4
External Clock and Trigger ................................................................. 8
3 The DAC subfunction ............................................................................... 9
3.1
DAC Hardware features ..................................................................... 9
3.1.1
Analog output specifications ............................................................ 9
3.2
DAC Memory Modes .......................................................................... 9
3.2.1
Memory Mode 0: Memory disabled ................................................... 10
3.2.2
Memory Mode 1: Single memory mode .............................................. 10
3.2.3
Memory Mode 2: Interleaved memory mode ....................................... 10
3.3
Available Sample Rates ................................................................... 11
3.4
External Clock and Trigger ............................................................... 12
3.5
Reconstruction filter ...................................................................... 12
4 The Digital I/O Port subfunction ............................................................... 14
4.1
Digital I/O specifications ................................................................. 14
5 The Scaler / Preset Scaler subfunction ....................................................... 15
5.1
SPS Hardware features .................................................................... 15
5.2
SPS specifications .......................................................................... 15
5.3
SCA operating modes ...................................................................... 16
5.4
PSC operating modes ...................................................................... 17
6 The Stepper Motor Controller subfunction ................................................... 19
6.1
STM Specifications ......................................................................... 19
6.2
STM Operating Modes ..................................................................... 19
7 The Pulse Width Modulation subfunction ..................................................... 21
7.1
PWM Specifications ........................................................................ 21
7.2
PWM Operating Modes..................................................................... 22
8 The Quadrature / Event counter subfunction ................................................ 24
8.1
QC Hardware features .................................................................... 24
8.1.1
Quadrature input specifications ...................................................... 24
8.2
QC Operating Modes ....................................................................... 25
TUeDACS NanoGiant Hardware Specifications
1

9 Trigger Modes ..................................................................................... 26
TUeDACS NanoGiant Hardware Specifications
2

The TUeDACS NanoGiant is a multi-purpose interface specifically designed for use in realtime closed-loop motion control systems.
The NanoGiant consists of two 16-bit DA converters, two 16-bit AD converters, a generalpurpose 16-bit I/O port, two quadrature / event counters and two stepper motor controllers and 4 independent clock signal generators. Two independent USB Software
Triggers which can serve as a timebase for the aforementioned functions.
The TUeDACS NanoGiant communicates with the host computer by means of a USB 2.0 connection.
The main features of the TUeDACS/1 NanoGiant are:
 2 independent analog input channels (ADCs) with 16 bit ADC resolution, a selectable input range (optional), a low-pass filter (optional) and two data memories per channel, which allow for continuous data acquisition at up to 100 kHz;
 2 independent analog output channels (DACs) with 16 bit resolution, -10 to 10 Volt output range, an optional signal reconstruction filter and two data memories per channel, which allow for continuous operation at up to 100 kHz;
 2 independent 32-bit Quadrature / Event Counters (QC), which can be configured as a single-ended or differential quadrature counter or as a single-ended event counter;
 16-bit general purpose Digital I/O port (DIO);
 2 independent Pulse Width Modulation (PWM) controllers with 25 ns resolution;
 2 independent stepper motor outputs (STM), each providing a direction and a step signal;
 2 independent 32 bit scalers (SCA) with 100 MHz maximum count frequency;
 2 independent 32 bit preset scalers (PSC) with 62.5 MHz maximum count frequency;
 4 independent software selectable clock signal generators with 40 MHz maximum frequency;
 2 independent USB software triggers, useful in closed-loop motion control systems to sync input/output timing;
 Special facilities for closed loop applications: up to 4 kHz closed loop frequencies.
This document only describes the hardware features of the NanoGiant, and does not mention how to use them. This is described in the software manual which can be found here . Software interfaces to C, LabView and Matlab/Simulink are available or will be made available in the future.
TUeDACS NanoGiant Hardware Specifications
3

This chapter describes the two ADC channels of the NanoGiant. The hardware features as well as the software-selectable operating modes are discussed.
The block diagram of one ADC channel is shown in Figure 1.
Analog in
Programmable
Gain Amplifier
Programmable
Low-Pass
Input Filter
16 bit ADC
PGA
Gain
Cutoff
Frequency
Figure 1: Block diagram of an ADC channel.
Two ADC channels (1 and 2) optionally have a programmable gain amplifier and a software programmable low-pass input filter. Two ADC channels (3 and 4) are optional. Channels 3 and 4 are differential, but can be configured as single-ended using the software.
The analog inputs, located on the Rear panel of the NanoGiant, have the following specifications:
 available through BNC connectors
 input voltage range -10 Volt .. +10 Volt
 16-bit resolution (305 μV for the range -10 volt .. +10 volt)
 input impedance 100k ohm
 differential inputs if a PGA is used (10M to GND)
 single-ended inputs if no PGA is used
 protected against over-voltages +/- 40Volt
TUeDACS NanoGiant Hardware Specifications
4

The gain can be selected using the software. In the implementation of the NanoGiant with
PGA, the selectable voltage ranges are:
Voltage Range
-10 V .. +10 V
-1 V .. +1 V
-0.1 V .. +0.1 V
Ideal resolution
305 μV
30.5 μV
3.05 μV
-0.01 V .. +0.01 V 0.305 μV
Also if there is no PGA, the gain is software selectable, with the following options:
Voltage Range
-10 V .. +10 V
-5 V .. +5 V
0 V .. +10 V
0 V .. +5 V
Ideal resolution
305 μV
152.5 μV
152.5 μV
76.25 μV
The low-pass input filter can be used for anti-aliasing and consists of one 8 th filters with a software selectable cutoff frequency f cutoff
order elliptic
in the range 0.763 Hz to 12 kHz.
Typical response characteristics of the filter are:
 20dB attenuation at 1.2 f cutoff
 52dB attenuation at 1.4 f cutoff
 70dB attenuation at 1.2 f cutoff
The cutoff frequency can be selected for each ADC channel individually.
The possible cutoff frequencies are given by: f cutoff
= 4 · 10
5
/ N filter
, where N filter
is an integer in the range 33 through 524287.
The operation of the NanoGiant ADC channels depends on the selected Memory mode.
With these Memory modes, it is possible to enable or disable the use of memories, and to control how they are used. When memories are not used, each recorded sample has to be read individually by the host computer, before recording a new sample. The memory mode can be selected for each channel individually.
In each Memory mode, the moment at which the ADC conversion starts depends on the
selected Trigger mode. The available trigger modes are treated in chapter 9.
Available Memory modes are:
TUeDACS NanoGiant Hardware Specifications
5

0.
Memory disabled;
1.
Single sweep memory mode;
2.
Continuous memory mode.
In this mode, an ADC channel does not use any memory. A sample is recorded when a
trigger of the selected type occurs (see chapter 9). This sample should be read by the host
pc, before the next conversion is triggered, or else the stored sample is overwritten.
An ADC channel configured in Memory Mode 1 uses one memory for single sweep operation. When trigger mode is selected, acquisition starts when one of the triggers of
chapter 9 occurs, after the NanoGiant ADC channel has been enabled by the software
program. When trigger mode is disabled, acquisition starts immediately after enabling the channel. Acquisition automatically stops after a cycle of samples has been recorded.
The cycle length can be defined by the software program and has a maximum of 2048 samples. During the measurement cycle, the acquired data is stored in the memory. When the cycle has completed, operation stops, the channel must be disabled and the recorded data should be read using the software. After that, the channel must be enabled again by the software, and a new sweep is recorded on the next trigger.
Enable Trigger
Disable
Enable Trigger
Acquired data
(memory 0)
Acquired data
(memory 0)
Figure 2: Acquired data in Memory mode 1. Note that when no trigger mode is selected, Enable and trigger will coincide.
An ADC channel configured in Memory Mode 2 uses interleaved memories to operate continuously. When trigger mode is selected, acquisition starts when one of the triggers of
chapter 9 occurs, after the NanoGiant ADC channel has been enabled by the software
program. When trigger mode is disabled, acquisition starts immediately after enabling the channel.
TUeDACS NanoGiant Hardware Specifications
6

Acquisition takes place in cycles. The cycle length can be defined by the software program and has a maximum of 1024 samples. During one measurement cycle, the acquired data is stored in one of the two available memories. When the cycle has completed, a new cycle is started immediately, and the newly acquired data is stored in the other memory. During the new cycle, the data stored in the previously active memory should be read by the software program. When the second cycle has ended, storage switches to the first memory again, etcetera. If the data from the previous cycle, stored in this memory, was not yet read by the software, an error occurs and data acquisition stops.
Acquisition stops after the NanoGiant has been disabled by the program and the measurement cycle in progress has completed, or when an error occurs.
Enable Trigger
Acquired data
(memory 0)
Acquired data
(memory 1)
Figure 3: Acquired data in Memory mode 2.
Etc.
The sample rates for channels operating in Memory modes 1 and 2 can be set using the software. In Memory mode 0, each individual sample is triggered, so the sample frequency is determined by the frequency of that trigger.
There are two modes of selecting sample rates, depending on whether Enhanced Clock
Mode is enabled:
 Enhanced Clock Mode is Disabled. The user can choose from 16 sample rates in the range 12.5 Hz to 100 kHz. See software documentation for available frequencies.
 Enhanced Clock Mode is Enabled. The sample rate is defined by:
Sample rate = 40 MHz / SampleRateIndex , where SampleRateIndex must be between 400 and 65535.
TUeDACS NanoGiant Hardware Specifications
7

For a channel in Memory mode 1 or 2, External Trigger Mode can be selected. When this is the case, an external trigger signal can be applied to pin 10 (for channel 1) or pin 11 (for
channel 2) of the PSC/SCA/STM connector, shown in Figure 11 on page 16. The trigger
signal level must be TTL-compatible.
When External Trigger Mode is selected, the trigger modes described in chapter 9 do not
apply anymore for the selected ADC channel(s).
For a channel in Memory mode 1 or 2, External Clock Mode can be selected. When this is the case, an external clock signal can be applied to pin 22 (for channel 1) or pin 23 (for
channel 2) of the DIO connector, shown in Figure 9 on page 14. The clock signal level must
be TTL-compatible.
When External Clock Mode is selected, the sample rates described in the previous section do not apply anymore.
TUeDACS NanoGiant Hardware Specifications
8

This chapter describes the two DAC channels of the NanoGiant. The hardware features as well as the software-selectable operating modes are discussed.
The block diagram of one DAC channel is shown in Figure 4.
Data
16-Bit
DA
Converter
Analog
Out
Figure 4: Block diagram of the DAC sections with extrapolation filter disabled.
The analog outputs, located on the front panel of the NanoGiant, have the following specifications:
 available through BNC connectors
 single-ended outputs
 output voltage range -10 Volt .. +10 Volt
 16-bit resolution (305 μV)
 output current max. +/- 6 mA
 during a power-on sequence of the NanoGiant, the DAC outputs are at an output level of 0.0 volts
The operation of the NanoGiant DAC channels depends on the selected Memory mode.
With these Memory modes, it is possible to enable or disable the use of memories, and to control how they are used. When memories are not used, each output value has to be written individually by the host computer.
In each Memory mode, the moment at which the DAC conversion starts depends on the
selected Trigger mode. The available trigger modes are treated in chapter 9.
Available Memory modes are:
0.
Memory disabled;
1.
Single memory;
2.
Interleaved memory.
TUeDACS NanoGiant Hardware Specifications
9

In this mode, memories for both channels are disabled. Each individual output value must be written using the software. The new value is applied to the analog output when a
trigger of the selected type occurs (see chapter 9), or immediately if trigger mode 0 is
selected. If no new value is written, before the next trigger occurs, the output remains at the same level.
A DAC channel configured in Memory Mode 1 uses one memory. The array of DAC samples must be written to the DAC memory before enabling the channel. After enabling, the DAC starts playing the data at a chosen sample rate when a trigger of the selected type occurs
(see chapter 9). When Trigger mode 0 is selected, data playback starts immediately after
enabling the channel. Using the software, Repeat Count can be enabled. When it is enabled, the array is looped a selectable number of times, or indefinitely. At any time, data playback can be disabled. When this happens, the current cycle is finished before operation stops.
The memory of one DAC channel can store a maximum of 2048 samples.
Enable Trigger
Output data Output data
Figure 5: Data playback in Memory mode 1. In this case, the Repeat Count is 2.
A DAC channel configured in Memory Mode 2 uses two memories to operate continuously.
An array of DAC samples must be written to the first DAC memory before enabling. After enabling, the DAC starts playing the data at a chosen sample rate when a trigger of the
selected type occurs (see chapter 9), after the NanoGiant DAC has been enabled by the
software program. When trigger mode is disabled, acquisition starts immediately after enabling the channel.
The data in the first memory is looped, until a Memory Switch occurs, after which data from the second memory is looped, and so on. Before a Memory switch occurs, new data must have been written to the other memory, or else an error will occur.
TUeDACS NanoGiant Hardware Specifications
10

When Memory switches occur, depends on the selected Memory Switch Mode. Each Memory
Switch Mode corresponds to one of the available triggers, described in chapter 9. When
Memory Switch Mode 0 is selected, the memories are switched when the Switch Memory function from the software is called. In the other Memory Switch modes, the memories are switched when a trigger of the corresponding type occurs.
At any time, the current cycle is finished before the memories are switched.
At any time, data playback can be disabled. When this happens, the current cycle is finished before operation stops.
One memory of one DAC channel can store a maximum of 1024 samples.
Enable Trigger Switch Switch
Output data
(memory 0)
Output data
(memory 1)
Figure 6: Acquired data in Memory mode 2.
Etc.
The sample rates for channels operating in Memory modes 1 or 2 can be set using the software. In Memory mode 0, each individual sample is triggered, so the sample frequency is determined by the frequency of that trigger.
There are two modes of selecting sample rates, depending on whether Enhanced Clock
Mode is enabled:
 Enhanced Clock Mode is Disabled. The user can choose from 23 sample rates in the range 25 Hz to 10 MHz. See software documentation for available frequencies.
 Enhanced Clock Mode is Enabled. The sample rate is defined by:
Sample rate = 40 MHz / SampleRateIndex , where SampleRateIndex must be between 400 and 65535.
TUeDACS NanoGiant Hardware Specifications
11

For a channel in Memory mode 1 or 2, External Trigger Mode can be selected. When this is the case, an external trigger signal can be applied to pin 19 (for channel 1, or both channels in parallel mode) or pin 20 (for channel 2) of the Input/Output Port (DIO). The trigger signal level must be TTL-compatible.
When External Trigger Mode is selected, the four Trigger modes described in chapter 9 do
not apply anymore for the selected DAC channel(s).
For a channel in Memory mode 1 or 2, External Clock Mode can be selected. When this is the case, an external clock signal can be applied to pin 24 (for channel 1) or pin 25 (for channel 2) of the Input/Output Port (DIO). The clock signal level must be TTL-compatible.
When External Clock Mode is selected, the sample rates described in the previous section do not apply anymore.
When External Clock Mode is not selected, the internal clock signal is applied to pin 24 (for channel 1) or pin 25 (channel 2).
IMPORTANT: When one of the DAC Memory modes 1 or 2 and External Trigger mode is
selected, the IOP pins 19..20 can not be used for other purposes anymore. Figure 7 shows
the function of each pin in this case.
D
G
N
D
D
G
N
D
D
9*
D
8*
D
G
N
D
D
7*
D
6*
D
5*
D
4*
D
3*
D
2*
D
1*
D
0*
13 12 11 10 9 8 7 6 5 4 3 2 1
25 pin FEMALE
Delta connector
Front View
25 24 23 22 21 20 19 18 17 16 15 14 ut
D
C lo ck
In
/O
C lo ck
In
A
C
2
C
1
/O ut
D
A
/O ut
C
2
A
D
/O ut
C lo ck
In
C lo ck
In
E
A
D
C
1 xt er na
D
G
N
D l T rig ge r D
A
C
2
E xt er na l T rig ge r D
A
C
1
D
13
*
-S up pl ie r
+5
V
D
12
*
D
11
*
D
10
*
Figure 7: Alternative pin assignment of the DIO for External Trigger Mode.
DAC signal reconstruction is important when using the NanoGiant in closed loop control applications, and for signal generation use. Signal reconstruction is only available in
Memory Mode 0 (memory disabled).
In Figure 8, at the equidistant time moments t
1
, t
2
, t
3
, etc, the DAC receives analog output values from the control algorithm (running on the host computer). It is easily seen that there is a delay. In theory, the delay in the control loop can be reduced by increasing the
TUeDACS NanoGiant Hardware Specifications
12

sample rate of the entire control system. However, this solution will result in many practical problems. y
4 y
3 y
2 y
1 t
1 t
2 t
3 t
4
Figure 8: DAC output signal without reconstruction; the smooth curve shows the desired signal.
A solution to this problem is signal reconstruction. A reconstruction filter improves the response of the control loop as the analog DAC output signal can be updated at a higher rate than the basic ‘sample rate’ of the control algorithm.
(More coming soon)
TUeDACS NanoGiant Hardware Specifications
13

The DIO is a 16-bit general purpose digital input/output. It has 16 pins, which can individually be set to either input or output mode using the software.
The input and output port can be triggered separately using one of the trigger modes listed
in chapter 9. When transparent trigger mode is selected, reading the input port returns
the current input values, and writing the output port immediately sets the new output values.
The IOP connector has the following specifications:
 inputs/outputs available through 25-pin female D-edge connector
 TTL inputs, TTL compatible signal levels
 Input/Output is low active: o 1 is logic LOW level (< 0.5 volt) o 0 is logic HIGH level (5 volt)
 tri-state TTL outputs
 outputs use 74LCX125M output buffers o V
H
: I out
= -0.5 mA o V
L
: I out
= 24 mA
The pin configuration of the IOP connector is given in Figure 9. The input/output pins are
indicated by D0 * .. D15 * . When External Trigger mode is selected for a DAC in memory
mode 1 or 2, pins 19 and 20 are sacrificed and the configuration shown in Figure 7 on page
12 is valid.
D
G
N
D
D
G
N
D
D
9*
D
8*
D
G
N
D
D
7*
D
6*
D
5*
D
4*
D
3*
D
2*
D
1*
D
0*
13 12 11 10 9 8 7 6 5 4 3 2 1
25 pin FEMALE
Delta connector
Front View
25 24 23 22 21 20 19 18 17 16 15 14
C lo ck
In
/O ut
D
A
C lo ck
In
C
C
2
/O ut
D
A lo ck
In
C
C
1
/O lo ut
A
D
C
2 ck
In
/O ut
A
D
C
1
D
G
N
D
D
15
*
D
14
*
D
13
*
+5
V
-S up pl ie r
D
12
*
D
11
*
D
10
*
Figure 9: Pin configuration of the NanoGiant DIO.
TUeDACS NanoGiant Hardware Specifications
14

This chapter describes the two Scaler (SCA) channels and the two Preset Scaler (PSC) channels of the NanoGiant, which together are referred to by Scaler / Preset Scaler (SPS).
The hardware features as well as the software-selectable operating modes are discussed.
The block diagram of one Scaler and one Preset Scaler channel is shown in Figure 10. The
Scaler and Preset Scaler can operate completely independent of each other, but they are shown in one diagram because the Gate Out signal of a Preset Scaler can be selected as
Gate source for a Scaler channel. The Gate Out of Preset Scaler channel 1 is then internally connected to Scaler channel 1, and similar for channel 2.
Clk In
Start In
Preset Scaler
Stop Out
Gate Out
Gate In
Clk In
Ext Gate In
Scaler
Figure 10: Block diagram of a NanoGiant SCA and PSC channel section.
The SPS has the following input/output specifications:
 available through 25-pin male D-edge connector
 TTL inputs/outputs, TTL compatible signal levels
 Input/Output is high active : o 1 is logic HIGH level (3.3 volt) o 0 is logic LOW level (< 0.5 volt)
 Preset Scaler outputs use 74LCX125 output buffers o V
H
: I out
= -24 mA o V
L
: I out
= 24 mA
The pin assignment of the 25-pin connector, which is also used for the STM, is shown in
Figure 11.
TUeDACS NanoGiant Hardware Specifications
15

1 2 3 4 5 6 7 8 9 10 11 12 13
14 15 16 17 18 19 20 21 22 23 24 25
Figure 11: Pin configuration of the NanoGiant SPS (SCA and PSC) and STM.
The Scaler is used to count clock pulses on an internal or external Clock signal. A Scaler channel operates as follows: when the channel is enabled by the software and the
(selected) Gate signal is HIGH, the counter is incremented each time a clock pulse occurs at Clk In. The counter is only reset when by a clear command from the software. The current count value can be obtained at any time, using the software.
One of the three following signals must be selected as Gate signal:
 The External Gate In signal, located on the connector;
 The Enabled state of the Scaler; when this is selected, the gate signal is always assumed to be HIGH, so the channel only needs to be enabled in order to count pulses;
 The Gate Out signal of the Preset Scaler with the same channel index, which is internally connected.
For the Clock signal, the user can choose between an external clock, which must be connected to the Clk In input, or an internal clock with a selectable frequency of 100MHz,
10MHz, 1Mhz or 100kHz.
In addition to the current count value of the Scaler, the so-called Intermediate Count
Value can also be obtained at any time using the software. This is the count value the
Scaler had at the last time an event took place at the Preset Scaler. This can be useful in some cases, for example when the Scaler and Preset Scaler are used together as a
Timer/Counter unit.
TUeDACS NanoGiant Hardware Specifications
16

The Preset Scaler can be used to count a selectable number of events, or can be used to generate programmable time intervals (frequency divider).
The two main operating modes are:
 Event counter mode. In this mode, after the PSC is started, it counts down from a selected preset value every time a clock pulse occurs. During countdown, the Gate Out signal is HIGH. When the counter is 0 and a new clock pulse occurs, counting stops and the GATE output is LOW again. A pulse with a width of one clock period is then
generated on the STOP OUT output. This is visualized in Figure 12.
T clock
Clock signal
Start T = N preset
x T clock
Gate Out
T clock
Stop Out
N preset
= 5
Figure 12: Operation of the Preset Scaler in Event counter mode.
 Event generator mode. In this mode, the PSC can be used as a frequency divider.
After counting down from N preset
+1, a pulse with a width of one clock period is generated at Stop Out. After that, counting starts again immediately. So the period of the Stop Out signal is (N preset
+1)*T clock
. The continuous operation continues until the
channel is disabled. This is visualized in Figure 13.
T clock
Clock signal
Start
T = (N preset
+1) x T clock
T clock
Stop Out
N preset
= 3
Figure 13: Operation of the Preset Scaler in Event generator mode. Gate Out is not used.
TUeDACS NanoGiant Hardware Specifications
17

In even counter mode, the channel must be started for each countdown sequence. In event generator mode, the channel must be started only once. Before a channel can be started for the first time, it must be enabled by the software. After that, the way of starting depends on whether External Start Mode is selected:
 If not selected, the countdown is started when a software trigger is applied. This can be a trigger for the PSC channel only, or one of the common triggers, as described in
chapter 9.
 If selected, the countdown is started when the Start In input becomes HIGH. In Event
Generator mode, the continuous operation is stopped when the START IN signal becomes LOW.
At any time, the operation is stopped when the channel is disabled by the software.
For the Clock signal, the user can choose between an external clock, which must be connected to the Clk In input, or an internal clock with a selectable frequency of 100MHz,
10MHz, 1Mhz or 100kHz.
Also for the Preset Scaler, the Intermediate Count Value can be obtained at any time. In this case it is the count value the Preset Scaler had at the last time an event took place at the Scaler.
TUeDACS NanoGiant Hardware Specifications
18

This chapter describes the two Stepper Motor controller (STM) channels of the NanoGiant.
The STM can be used to control two stepper motor drivers, independently. The number of pulses, and the pulse period and width are software-selectable.
The STM has the following output specifications:
 available through 25-pin male D-edge connector
 TTL inputs/outputs
 output is high active : o 1 is logic HIGH level (3.3 volt) o 0 is logic LOW level (< 0.5 volt)
 outputs use 74LCX125 output buffers o V
H
: I out
= -24 mA o V
L
: I out
= 24 mA
 Endstop inputs can be either high or low active (software selectable).
The pin configuration of the STM is shown in Figure 11 on page 16, as the STM shares its
connector with the SPS.
The STM has two software-selectable operating modes:
 Normal mode: For clockwise operation, the Direction output is LOW and for counterclockwise operation it is HIGH. Pulses are generated on the Pulse output,
where each pulse corresponds to a step of the motor. This is shown in Figure 14.
Start, 3 steps,
Clockwise
Start, 4 steps,
Counter-Clockwise
Direction Output
Pulse Output
Width Delay
Figure 14: STM channel operating in normal mode.
TUeDACS NanoGiant Hardware Specifications
19

 Enhanced mode: For clockwise operation, the Direction output is LOW and pulses are generated on the Pulse output. For counterclockwise operation, the Pulse output is
LOW and pulses are generated on the Direction output. This is shown in Figure 15.
Start, 3 steps,
Clockwise
Start, 4 steps,
Counter-Clockwise
Direction Output
Pulse Output
Width Delay
Figure 15: STM channel operating in enhanced mode.
When selecting the mode using the software, the user also sets the pulse width and pulse delay, in units of 10 μs. The number of steps to make, and the direction, must be provided each time a pulse sequence is started. A STM channel does not need to be enabled and does not use common software triggers or external triggers. To see whether the STM channel is busy, the status can be obtained using the software. A currently running pulse sequence can always be aborted by the user.
Using the software, the Endstop inputs of a STM channel can be enabled. By connecting these to the Endstop outputs of the Stepper Motor to be controlled, the Endstop status is obtained every time the status of the STM is read by the software.
There are two Endstops for each STM channel:
 Endstop Clockwise: this signal is HIGH when the Stepper Motor is currently at its limit in the Clockwise direction.
 Endstop Counterclockwise: this signal is HIGH when the Stepper Motor is currently at its limit in the Clockwise direction.
The Endstop status, which is read by the software, consists of:
 The current state of the Endstop signal.
 Whether a new Endstop has been detected since the previous status acquisition. This way, an Endstop is detected even when the Stepper Motor has moved back from its end position.
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This chapter describes the two Pulse Width Modulation channels of the NanoGiant.
The PWM subfunction can be used to generate 2 independent pulse width modulated
(PWM) signals. A PWM signal is typically used for motion control applications, such as servo motor control.
The PWM has the following output specifications:
 available through 15-pin female D-edge connector
 TTL outputs
 Output is high active : o 1 is logic HIGH level (3.3 volt) o 0 is logic LOW level (< 0.5 volt)
 outputs use 74LCX125 output buffers o V
H
: I out
= -24mA o V
L
: I out
= 24 mA
8 7 6 5 4 3 2 1
15 14 13 12 11 10 9
Figure 16: Pin configuration of the NanoGiant PWM subfunction (PWM and Direction outputs) and QC subfunction (CLK A1, CLK A2 and REF inputs).
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The NanoGiant supports 2 types of PWM signal generation:
 Locked anti-phase PWM;
 Sign/magnitude PWM.
Locked anti-phase PWM consists of a single, variable duty-cycle signal in which both direction and amplitude information is encoded. The duty cycle is defined as the fraction of time that the output signal is high. A 50% duty-cycle PWM signal represents zero drive
(no rotation). A less then 50% duty-cycle signal represents e.g. a clockwise rotation, and a less then 50% duty-cycle signal then represents a counter-clockwise rotation. The absolute
value of the duty-cycle represents the average drive. See Figure 17.
No Rotation
Clockwise
Rotation
Counter-
Clockwise
Rotation
Figure 17: Locked anti-phase PWM.
Sign/magnitude PWM consists of separate direction (sign) and amplitude (magnitude) signals. The duty-cycle represents the absolute value of the magnitude signal and can be in the range 0% .. 100%. The absence of a pulse signal (duty-cycle 0%) represents zero drive.
See Figure 18.
Counterclockwise
Direction Clockwise
Medium Drive
Low Drive
TUeDACS
High Drive
Figure 18: Sign/manitude PWM.
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For both locked anti-phase PWM and sign/magnitude PWM, the pulse signal is determined by the timing parameters T
1
and T
2
, as shown in figure 11.3. The timing parameters T
T
2
are selected using the software.
1
and
T
1
PWM Signal
T
2
Figure 19: T
1
and T
2 values of the PWM signal.
The T
1 value and the Direction output level can be changed on the fly using the software.
When a new T
1
value is supplied, the output signal is updated at the end of the T
2
period, after the next selected trigger. There are four trigger modes available, described in
chapter 9. When trigger mode 0 is selected, the output signal is updated immediately at
the end of the current T
2
period.
Note that the direction signal is not used with Locked anti-phase mode; in that case it may be used as a general purpose digital output.
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This chapter describes the two Quadrature / Event Counter (QC) channels of the
NanoGiant.
The block diagram of one QC channel is shown in Figure 20.
32-Bit
Quadrature
Counter
Phase
Swap
Input Mode
Selection
A1+
A1-
Quadrature IN
A2+
A2-
Quadrature IN
Reference IN
Figure 20: Block diagram of a QC channel
The quadrature counter signals are applied to the A1+/A1- and the A2+/A2- inputs. The
input mode for these signals is software selectable, see section QC Operating Modes.
The software-selectable phase swap facility swaps the phase of the quadrature input signals of the quadrature counter, thereby effectively reversing the direction in which the quadrature counter counts.
The Quadrature / Event counter has the following input specifications:
 available through 15-pin male D-edge connector
 single ended inputs for A1 and A2 quadrature signals, or for A1 event signals
(software-selectable).
 TTL compatible signal levels
 power supply for quadrature encoder available on D-connector: 5 Volt, max. 150 mA, short-circuit protected
 A1 and A2 quadrature/event counter input signals have an input filter to suppress spikes with a maximum pulse width of 200 ns
The pin configuration of the QC is given in Figure 16 on page 21, as the QC shares its
connector with the PWM.
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The quadrature counters are used to count signals from position encoders or angular displacement encoders. A quadrature counter accepts 2 input signals, labeled A1 and A2, with a phase shift of +90 degrees or -90 degrees. A phase shift of +90 degrees results in a counter increment, a phase shift of -90 degrees results in a counter decrement. The following timing diagrams show when a counter is incremented/decremented:
+1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1
A1
A2
Figure 21: Quadrature counter incrementing
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
A1
A2
Figure 22: Quadrature counter decrementing
When a pulse occurs on the Reference input (REF), the current counter value (home position) is stored. This home position can be read using the software. The current counter value can also be read at any time using the software. When one of the trigger modes 1..3
described in chapter 9 is selected, reading the counter value with the software returns the
counter value at the last trigger.
The counter can be configured in event counter mode also. In this mode, the counter increments at the rising edge of a TTL pulse on A1, and A2 is not used. The counter never decrements.
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For some subfunctions of the NanoGiant (ADC, DAC, PWM, QC, PSC and both the input and output function of the DIO), operation is started/enabled when a selected trigger occurs.
For each subfunction, a choice must be made between a total of four ways of triggering:
 (1) No triggering (transparent trigger mode). The trigger occurs automatically when new data is written/read. This mode is not available for the PSC.
 Trigger mode. When trigger mode is enabled for a certain subfunction, triggering can be done in three different ways: o (2) Individual software trigger. A channel is triggered by calling a Software
Trigger function, specific for that subfunction. This is not available for the
DIO. o (3) Common trigger input. This trigger occurs when the Generate Common
Trigger Input function is called in the software. With this function, you supply a list of channels that need to be triggered. o (4) Common trigger output. This trigger occurs when the Generate Common
Trigger Output function is called in the software. With this function, you supply a list of channels that need to be triggered.
The common trigger input and output can be used to sync the operation of various subfunctions. When for instance the Common trigger input occurs, all subfunctions that have been selected for this trigger will input/output data at the same time.
In principle, both common triggers are interchangeable. It is however recommended to let all input devices, that have to operate simultaneously, use the common trigger input, and to let all output devices use the common trigger output.
These common triggers are typically useful in closed-loop motion control applications. In such an application, all output values will be changed at a certain point in the time loop, and the effects of these changes will be measured at a point later in the time loop, etc.
For some subfunctions (ADC and DAC in a memory mode other than 0, PSC, …) an external trigger can be selected. When this is the case, software triggers will have no effect.
The SCA and STM subfunction do not have trigger modes. The SCA doe not need one, because its function is to count external pulses. The STM is always transparently triggered.
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