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Wireless Chip Designer
Oct XX, 2006
Theme: Wireless-RF Testing
www.chipdesignmag.com/wirelesschipdesigner
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Today's Table of Contents:
1. XXX
2. 4G Wireless Broadband Initiative Announced
3. Turnkey Development And Test Solution Delivered
4. Test Solution Enables Faster Time-to-Yield
5. Agilent And Peregrine Team To Provide RFIC Design Tools
6. Jazz Semiconductor To Merge With Acquicor
7. ESL Platform Selected For SoC Design Challenge
8. Partnership Focuses On Advanced Noise Modeling
9. In-Depth Coverage Links
> Semiconductor Fabrics Need New Tools Approach
> Be Early With Power
10. New Books
11. Happenings -- Conferences
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1. Viewpoint - Exclusive
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Insert Editorial Here (Supplied by John Blyler)
Comments about this article? Share your thoughts by writing our editorial director:
jblyler@extensionmedia.com
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2. News
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4G Wireless Broadband Initiative Announced
Sprint Nextel Corporation is developing the first fourth generation (4G) nationwide
broadband mobile network based on the mobile WiMAX (Worldwide Interoperability for
Microwave Access) IEEE 802.16e-2005 technology standard. Working together with
Intel, Motorola and Samsung to incorporate WiMAX technology for advanced wireless
communications into consumer electronics devices, Sprint Nextel will develop not only
the nationwide network infrastructure, but mobile WiMAX-enabled chipsets as well. The
infrastructure and chipsets will be designed to support advanced wireless broadband
services for computing, portable multimedia, interactive and other consumer electronic
devices. The network will use Sprint Nextel's extensive 2.5-GHz spectrum holdings,
which currently covers 85 percent of the households in the top 100 U.S. markets.
Intel Corporation >> http://www.intel.com
Motorola >> http://www.motorola.com
Samsung >> http://www.samsung.com
Sprint Nextel Corporation >> http://www.sprint.com
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3. News
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Turnkey Development And Test Solution Delivered
Credence Systems Corporation has partnered with Integra Technologies to offer mixedsignal and RF application development support for design houses located in North
America. Integra is also expanding its RF and mixed-signal test capabilities with the
purchase of an additional Credence ASL 3000RF test system.
According to Integra, the rapid proliferation of wireless and RF capabilities in today's
computing and consumer electronics markets has created numerous opportunities for
emerging design houses with the right expertise. Many of these start-ups, however, lack
dedicated test resources and are not able to work with the larger test houses until product
demand reaches sufficiently high production volumes. The Credence/Integra partnership
is intended to provide such customers with a turnkey test solution to meet their needs
from design to low-volume production. Once a customer transitions to high-volume
production, Integra will then help facilitate the transfer of product testing to a test house
where they can still leverage the performance and cost advantages of Credence's systems.
Credence Systems Corporation >> http://www.credence.com
Integra Technologies >> http://www.integratechnologies.com
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4. News
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Test Solution Enables Faster Time-to-Yield
LogicVision’s SiVision Yield Analysis application – a test solution which enables faster
time-to-yield and improved end-product quality – has been adopted by Sequoia
Communications. SiVision is an automated, easy-to-use Yield Analysis environment that
provides second-generation data management, analysis and reporting capabilities.
SiVision's unique SmartPE infrastructure allows semiconductor companies to automate
their yield procedures and define data mining rules which automatically identify yield
limiters. The solution was selected by Sequoia Communications because of its powerful
automated data analysis and reporting capabilities, as well as its ease-of-use in
identifying and debugging yield issues. It will be used to automatically upload test and
foundry data as soon as it becomes available, and to automate data analysis during the
characterization, pre-production and volume production phases.
LogicVision >> http://www.logicvision.com
Sequoia Communications >> http://www.sequoiacommunications.com
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5. News
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Agilent And Peregrine Team To Provide RFIC Design Tools
Agilent Technologies today announced a multi-year, multi-site agreement in which
Peregrine Semiconductor has expanded its investment in Agilent Technologies' RFIC
design tools, designed to boost productivity and production yields. Peregrine has been
using a range of Agilent's RFIC tools, including Agilent's Advanced Design System
(ADS) Dynamic Link and RF Design Environment (RFDE) circuit simulation tools,
Ptolemy system design simulator, wireless test benches, and electromagnetic simulation
tools to successfully tape out advanced RFIC designs such as RF digital step attenuators,
PLL frequency synthesizers, passive mixers and prescalers. This core investment in
Agilent’s RF EDA technology will help make RFIC design more efficient and predictive,
resulting in decreased design spins, increased manufacturability and decreased overall
risk.
Agilent Technologies >> http://www.agilent.com
Peregrine Semiconductor >> http://www.peregrine-semi.com
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6. News
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Jazz Semiconductor To Merge With Acquicor
Jazz Semiconductor, an independent wafer foundry offering process technologies for the
manufacture of highly integrated analog and mixed-signal semiconductor devices for end
markets like wireless communications, has entered into a merger agreement with
Acquicor Technology. Under the terms of the agreement, Jazz will merge with a wholly
owned subsidiary of Acquicor in an all-cash transaction valued at $260 million, subject to
adjustment based on Jazz's working capital and for possible future contingent payments.
Following the merger, Jazz will become a wholly owned subsidiary of Acquicor and will
continue to operate as Jazz Semiconductor. Completion of the merger is expected to
occur in the first quarter of 2007.
Acquicor Technology >> http://www.acquicor.com
Jazz Semiconductor >> http://www.jazzsemiconductor.com
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7. International News
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ESL Platform Selected For SoC Design Challenge
Celoxica announced that its Toshiba MeP (Media Embedded Processor) Development Kit
has been selected by the Japanese VLSI Design and Education Center (VDEC) as the
design platform and environment for a nationwide digital media SoC design challenge.
This announcement is the result of years of collaboration and investment made by
Celoxica, Toshiba and VDEC into semiconductor solutions and system level design for
very complex System-on-Chip (SoC) design.
Celoxica’s Development Kit provides a comprehensive package of Embedded System
Level (ESL) design tools, programmable hardware platforms and utilities to help
designers develop high performance SoC designs. As well as offering MeP processor
Intellectual Property (IP), the kit is fully integrated into Toshiba’s MeP design flow to
enable the rapid creation and validation of complex designs from algorithmic models. As
part of VDEC’s design challenge, it will be used by teams of specialist SoC developers to
create award winning designs around Toshiba’s MeP architecture. After completion of
the challenge, VDEC expects to roll out the platform solution to over 150 Japanese
universities and 640 research groups who are part of the VDEC network.
Celoxica >> http://www.celoxica.com
Toshiba >> http://www.toshiba.com
VLSI Design and Education Center >> http://www.vdec.u-tokyo.ac.jp/English
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8. International News
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Partnership Focuses On Advanced Noise Modeling
The semiconductor foundry UMC, and Singapore's Institute of Microelectronics (IME),
have sealed a partnership to jointly develop RF modeling solutions for 90-nm
technologies. The newly formed joint development program encompasses two areas of
research: high frequency noise characterization and modeling for RF applications at
nanometer process technologies, as well as circuit modeling verification and validation
flow development based on IME's RF circuits and tests. Progress in these areas will help
facilitate the development of a Mixed Mode (MM)/RF circuit and modeling validation
methodology for advanced system-on-chip (SoC) applications. These resources will help
accelerate design-in and reduce risk for customers developing SoCs that incorporate RF
applications for wireless segments such as 3G, WLAN and Bluetooth.
Institute of Microelectronics >> http://www.ime.a-star.edu.sg
UMC >> http://www.umc.com
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9. In-Depth Coverage Links
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Innovation - the growth engine of the semiconductor industry - is showing a new trend
line in the fabric space. At one time in the mid-'80s, industry tracked custom design, gate
arrays, and application-specific integrated circuits (ASICs). ASICs became the fabric of
choice throughout the '90s. Nevertheless - new-generation semiconductor fabrics need
new tools approach. To learn more, read: “Semiconductor Fabrics Need New Tools
Approach.”
Chip Design Editorial Feature >>
http://www.chipdesignmag.com/display.php?articleId=567&issueId=17
Traditionally, costs associated with packaging and cooling have been the key drivers for
pulling power within an acceptable range. However, several other considerations are
driving the need for low power devices today. To learn more, read: “Be Early With
Power.”
iDesign Editorial Feature >>
http://www.chipdesignmag.com/display.php?articleId=613
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10. New Books
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Design and Characterization of Integrated Varactors for RF Applications
By Inigo Gutierrez, Juan Meléndez and Erik Hernández
ISBN: 0-470-02587-5
Publisher: Wiley-IEEE Press
Varactors are passive semiconductor devices used in electronic circuits, as a voltagecontrolled way of storing energy in order to boost the amount of electric charge
produced. In the past, the use of low-cost fabrication processes such as complementary
metal oxide semiconductor (CMOS) and silicon germanium (SiGe) were kept for
integrated circuits working in frequency ranges below the GHz. Now, the increased
working frequency of radio frequency integrated circuits (RF ICs) for communication
devices, and the trend of system-on-chip technology, has pushed the requirements of
varactors to the limit. As the frequency of RF applications continues to rise, it is essential
that passive devices such as varactors are of optimum quality, making this a critical
design issue. This book describes the physical phenomena that occur in passive devices
within standard IC fabrication processes. It presents information on the design of wide
band electrical varactor models (up to 5 GHz) which enable the accurate prediction of
device performance, proposes a specific methodology for the measurement of integrated
varactors, explains de-embedding techniques, and analyzes the confidence level and
uncertainty linked to the test set-up. It also examines the design of a voltage controlled
oscillator (VCO) circuit as a practical example of the employment of methods discussed
in the book.
Wiley-IEEE Press >> http://www.wiley.com/
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11. Happenings - Conferences
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GSPx Conference and Expo
October 30 - November 2, 2006
Santa Clara, CA
www.gspx.com/index.php/
4th International System-on-Chip
November 1-2, 2006
Newport Beach, CA
www.savantcompany.com/SoC4-Fall2006/main.htm
2006 ICCAD Conference
November 5-9, 2006
San Jose, CA
www.iccad.com
2006 Software Defined Radio Technical Conference and Product Exposition
November 13-17, 2006
Orlando, FL
www.sdforum.org
Electronica
November 14-16, 2006
Munich, Germany
www.global-electronics.net
WAMICON 2006 - IEEE Wireless and Microwave Technology Conference
December 4-5, 2006
Clearwater, FL
www.ee.eng.usf.edu/WAMI/conferences/2006
2006 IEEE International Electron Devices Meeting
December 11-13, 2006
San Francisco, CA
www.his.com/~iedm
2007 International CES
January 8-11, 2007
Las Vegas, NA
www.cesweb.org
Electronic Design and Solution Fair 2007 with FPGA/PLD Conference
January 25-26, 2007
Pacifico Yokohama, Kanagawa, Japan
www.edsfair.com
DesignCon 2007
January 29 – February 1
Santa Clara, California
www.designcon.com
Design Automation and Test in Europe (DATE)
April 16-20, 2007
Acropolis, Nice, France
www.date-conference.com
Read past issues of Chip Designer, FPGA Developer and Wireless Chip Designer eNewsletter:
http://www.chipdesignmag.com
WIRELESS CHIP DESIGNER e-NEWSLETTER CONTACTS
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Editor: Cheryl Ajluni
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Editorial Director: John Blyler
mailto:jblyler@extensionmedia.com
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