Numerical Analysis of the Affects of Line Edge Roughness
on Device and Chip Performance
1. Introduction
We propose to model and analyze effects of line edge roughness (LER) and line width roughness
(LWR)1 on device and chip performance for deep nanometer gate length devices. The goal of this
modeling will be the definition of electrical monitors for the characterization of LER in deeply
scaled MOSFET structures. During the course of this work, we are planning to build on our
existing device simulator tools [1-3] that include classical as well as quantum effects on mobile
carrier transport. Target device structures include N-MOSFETs, silicon-on-insulator MOSFETs,
and carbon nanotube embedded MOSFET structures.
As we approach sub-nanometer device lengths, even the slightest variations from the ideal device
dimensions are becoming important. In most cases, these variations cause degradations in device
and chip performance rendering traditional device scalability inapplicable in decananometer
MOSFETs. One of the main problems associated with nanometer-scale devices is the random
deviation of the line edges (especially of the MOSFET gate poly) from the initially laid out
straight line boundaries [4-10].
These random variations in line boundary positions have been present throughout the history of
semiconductor component technology. This problem has gone unnoticed until recently. However,
the non-scalable nature of the LER (as shown in Fig. 1 of [6]) means that the impact of LER
becomes more evident as we shrink device dimensions. For the upcoming technology nodes
(<90nm), variations in device length and width are expected to be comparable to ideal terminal
dimensions unless process scientists come up with new techniques to reduce these random
fluctuations. Thus, researchers need tools to understand the extent of the problem for a given
metrology technique, and characterize the effects of LER and LWR on device performance.
The standard way of characterizing LER involves a few steps: fabricating the poly lines, then
taking high resolution scanning-electron-microscope (SEM) images of these gate poly lines, next
empirically fitting the line edge roughness to a mathematical model suitable for use in device
simulators (and obtaining the 3-σ variation), and (finally) simulating the devices to determine the
variations in key performance parameters from the ideal devices that have straight lines.
Experimental characterization of LER requires transverse line width measurements of long poly
lines at some sampling period, d. We can distinguish two components of LER (based on d) for
analytical purposes: low and high frequency components corresponding to shorter and longer
sampling lengths, respectively. Low-frequency (or short-range LER) has a typical sampling
period of 1-2nm, whereas high-frequency or long-range LER can be attained using sampling
periods of 10nm and more. Short-range LER is associated with process conditions related to
lithography and resist. Long-range LER is caused by polysilicon surface roughness, mask making
processes and the implant or etch process tool[9].
It has been shown that LER can cause serious problems that adversely affect mostly the off-state
leakage current budget and short-channel effect control [4-10]. It may also result in negative
average threshold voltage shift, subthreshold slope degradation and erroneous device parameter
1
Note: we make a distinction between LER (single-boundary measurement) and LWR,
which is the result of random fluctuations of two boundaries.
1
extractions [10]. However LER does not significantly cause a change in on-current value due to
smoothing out of channel junctions by conventional spike-annealing, implantation scattering and
dopant diffusion [7-8].
Calculated results indicate that LER does not cause major problems down to 80nm gate lengths
[5]. However, LER and LWR become a problem for devices that have gate lengths shorter than
80nm [5]. When deliberately introduced, LER is measured to increase off-current threefold in
40nm or longer physical gate length devices [7]. As for LWR, for a 3-σ edge variation of 17nm
for an 80nm device design, various average values of key device parameters (threshold voltage,
off- and on- currents) are calculated to be independent of gate width. However, the variance is
observed to be proportional to the inverse square root of the gate width [4].
To simulate LER, we will build upon our previous work and that of other researchers
[1,2,3,4,5,6,8,10]. We expect to first extract the line-edge shape experimentally. Then we plan to
empirically fit the autocorrelation function power spectrum to the Fourier transform of the
measured data. Lastly, we will regenerate line edge roughness using inverse Fourier transform to
be used in device simulators. In 2-D simulators, they divide the 3-D device into N 2-D device
segments, then simulate each 2-D device, and later average the calculated device parameters out
to obtain the mean characteristics. This has been shown to agree well with the 3-D device
simulations [4]. It has been also claimed that 3-D device simulation will give unrealistically high
drive currents due to unduly high abrupt junction formations [10]. However others claim that,
even though it is time-consuming, the use of a proper mesh would give more realistic results in 3D simulations [4-6,8] and enable the inclusion of LER and LWR at the same time. We next will
show our device performance models that we plan to solve in 2-D and/or 3-D.
There are two goals to the current work. First, we will ascertain through modeling and through
fabrication, the impact of LER and LWR on device performance. Second, through simulation, we
will design test vehicles that emphasize the effect of these variations on device performance. The
goal of this phase of work is to ascertain whether LER and LWR model parameters can be
effectively extracted from MOSFET arrays.
2. Device Performance Model
To obtain LER and LWR effects on device and chip performance, we will build on our existing 2D device simulator tools [1-3], and develop a quantum device performance simulator based on
the quantum and semiconductor equations. The simulator will give us the terminal currentvoltage characteristics, as well as the electrostatic potential, current densities and carrier
concentrations at every point inside the device. The simulations will allow us to probe inside the
device, where measurements can not be performed. This numerical probing will allow us to
understand physical phenomena which occur inside the devices, and thereby provide information
on the expected characteristics, and how to improve the design and performance of future
devices.
Below we list the mathematical device equations on which the simulator will be based [1-3],
starting from the Poisson equation, followed by the electron continuity equation and hole
continuity equation, respectively.
 2  
q

 p  n  D
2
(1)
n 1
 .J n  GRn
t q
p
1
  .J p  GR p
t
q
(2)
(3)
Here the newly introduced variables  , n-p, Jn-p, D and GRn-p are electrostatic potential, electronhole concentrations, electron-hole current densities, net dopant concentration, and electron-hole
Shockley-Hall-Read net generation-recombination rates, respectively. We next define electronhole current densities Jn-p as follows:
n
J n  qnn   QM  HS
  n kT n
p
J p  qp p    QM  HS
   p kT p
(4)
(5)
We here symbolize electron-hole mobilities by  n  p . We also introduce two additional effective
potential terms QM and HS to account for the quantum and the heterostructure (if our device has
regions that are filled with different types of material) barrier effects, respectively. We next will
discuss how these two phenomena are taken care of by the effective potential terms starting from
the heterostructure effects.
For reference, we write HS , which for electrons and holes are respectively defined as follows [2]:
1
kT  n 
   Si   ln  Sio 

q
q  no 
(6)
1
kT  n 
  EG   Si  EGSi   ln  Sio 

q
q  no 
(7)
n
HS

p
HS

Here  is the electron affinity at a grid point on our device and is in reference to  Si . Here
bandgap EG, like  and no (intrinsic carrier concentration), refers to the same material in space.
We note that this formalism does not account for atomistic bonding details, which could give rise
to interface states and complicated junctions. These effects would likely be accounted for in the
present model through the Poisson and transport equations, the Fermi level and the mobility.
Solution of the 2-D MOSFET system requires proper handling of quantum phenomena. This is
due to the quantum well formed at the Si-SiO2 interface that causes band splitting, and lowers the
carrier concentration. (We also need to include heterostructure effects if other materials besides Si
are present in the MOSFET channel. In this case, heterostructure barriers emerge due to the
different bandstructures and electron affinities of the materials. A quantum well may also form at
these junctions due to the band-offsets.) Therefore we also solve for the quantum effects. To
resolve quantum effects, we utilize one of two methods; direct solution of the Schrödinger
equation or the density gradient formalism. Direct solution of the one-dimensional Schrödinger
equation along the channel direction for each line starting from the interface and going down the
substrate necessitate the inclusion of the following equations in addition to Eqns. (1)-(5):
3
d 2 i ( y)
Ei i ( y)   *
 q ( x, y) i ( y)
2m
dy 2
 EF  Ei  
m*kT

2
kT
nQM 

ln
1

e

i


 2 i


2
(8)
(9)
Here Ei, EF and  i are the sub-band energies, Fermi level and wave functions, respectively.
Above we list the Schrödinger equation followed by the population equation that gives the
density of electrons in the channel by summing contributions from different subbands. In this
formalism, effective quantum potential QM can be written as a built-in potential term as follows:
QM 
kT  nQM 
ln 

q  nCL 
(10)
We sometimes use the density gradient formalism instead of the direct solution of the
Schrödinger equation to include 2-D quantum effects and lower the simulation time. This
formalism has been shown to resolve confinement and band-to-band tunneling effects [2].
According to the density gradient theory, effective quantum potential QM can be written as
follows:
QM 
2 2
12q n
 1 2 n 1 2 n 



2
m y 2 
 m x
(11)
Here x is parallel to the MOSFET channel, and y is normal to x.
To obtain device performance details, we first solve Eqns. (1)-(3) with the help of Eqns. (4)-(5)
by setting the quantum effective potential term to zero ( HS is zero if only Si and channel
dopants are present in the MOSFET channel.). The solution will be obtained by first discretizing
the equations, thereby transforming the coupled nonlinear system of partial differential equations
into a system of algebraic equations. We then solve the nonlinear algebraic system numerically
using a combination of complex algorithms involving sparse matrix algebra, and iterative
methods. Once we obtain the classical solution that does not include confinement effects, we use
it as the initial guess for solving Eqns. (8) and (9), or Eqn. (11) (depending on the method we use)
in addition to Eqns. (1)-(5). Therefore, we obtain device performance characteristics including
current-voltage curves and profiles of electrostatic potential and carrier concentrations inside the
device.
For this research, we will extend our device simulator to resolve effects of line edge roughness by
either simulating N 2-D devices or one 3-D device with the gate terminal displaying line edge
roughness.
3. Device Fabrication. The University of Maryland maintains on-going chip fabrication activities
through the MOSIS foundry process. Unfortunately, there are no sub-90nm processes available
through MOSIS. We do, however, have access to the full Cadence design suite – the major
computer-aided design (CAD) tool of the semiconductor industry. Our plan is to integrate our
work with experimental lines, such as the Lincoln Laboratories 3D IC/SOI line. We have
privileged access to those lines through on-going collaborative efforts with the Department of
4
Defense (DoD). We already possess the Lincoln Labs product design kit (PDK). This is the
essential interface between CAD and fabrication. We are currently fabricating 3D IC structures
on this product line. Experimental devices with line width less than 90nm are available through
this service.
III. Statement of Work
We are proposing a three-year effort aimed at characterizing the impact of LER and LWR on
90nm, 65nm and 30nm technology nodes. During the course of this work,
1. We will model the impact of LER and LWR for MOSFET components of various
geometries at the 90nm, 65nm and 30nm nodes.
2. We will design transistor arrays of various length to width ratios in these node
generations
3. We will fabricate these test vehicles using our internal CAD tools in conjunction with a
partner experimental fabrication facility (such as Lincoln Laboratories and/or NIST).
4. We will extract base performance parameters from these arrays and compare the results
with our models
5. We will modify our models as necessary to achieve closest agreement with experimental
data.
6. We will optimize the array design to ascertain the degree to which electrical
characterization serves to parameterize the LER and LWR statistical parameter base.
IV. Budget: $125K
1 Post-doctoral fellow
2 man-months of senior faculty time for supervision
Travel expense
Computer up-grades.
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