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Sample Problems
Short Answer
1. If CMOS circuits are built with NAND and NOR gates, why do we design the circuits
using AND and OR gates?
It is easier to understand the functionality of a circuit without the multiple inversions you
get with NAND and NORgates.
2. What do we know about a logic circuit that has two inverting circles back to back (i.e.
directly connected to each other).
They cancel each other out and can be removed.
3. A signal of the form DOOR_OPEN(H) is what type of signal?
Asserted-high (high-true) (i.e. when the door is open the signal is high).
4. DeMorgan's THm. Allows us to convert an AND gate into what type of gate?
A NOR gate with inverted inputs.
5. Generally, how do we convert from AND/OR to NAND/NOR circuits?
Insert back to back inverting circles between gates (i.e. cancel each other out and have no
effect on overall logic). Starting at the outputs and going towards the inputs, convert
every second layer of logic into its DeMorgan's equivalent (i.e. an OR gate with inverted
inputs becomes a NAND and an AND gate with inverted inputs becomes a NOR).
6. What is the purpose of dependency notation?
It provided us with a precise compact graphical notation to describe complex ICs and
circuit functions.
7. Draw a 4-1 multiplexer using dependency notation.
8. Using dependency notation, how can tell the difference between a contol signal and a
data signal?
Control signals start with a letter, while data signals start with a number.
9. Draw the circuit block using dependency notation for the function F = (A * B) + C
10. In dependency notation an XOR function is given the letter N which stands for
negate. Why is this?
An XOR can be considered a controlled negator (i.e. if one input is held low the other
input is passed to the output, if one input is held high the output is a negated (inverter)
version of the other input.
11. What is the purpose of the control (T -shaped) block?
If an IC that has several identical subsections controlled by some common signals (e.g. a
common clock), the common signals are fed into the control block. The control block
tells us that all sections below it are controlled by its input signals.
12. What is the meaning of enable dependency on a data signal output?
The enable dependency mean that the output can be put in a tri-state or high impedance
state which is used for signals that form a common bus.
13. Using dependency notation, how do we represent multiple dependencies?
We use a “,” (anding of dependencies) or a “/” (oring of dependencies).
14. Give the dependency notation for a 4 bit edge triggered register (using D flip-flops)
with tristate outputs.
15. What are the common types of latches/flip-flps that are used today?
RS latches, D latches/flip-flops, T flip-flops
16. What is the difference between a latch and a flip-flop?
Flip-flops are triggered only on the clock edge (i.e. only accept data on the clock edge)
17. What is the function of an enable signal on a T flip-flop?
It allows the T-flip-flop to either toggle on not.
18. Draw the dependency notation for a D latch with active low clock . Draw its timing
diagram and show when it is in transparent mode and when it is in latch mode.
19. Draw a timing diagram showing the operation of a negative edge tirggered D flipflop.
20. What do we mean when we say a set dominant RS latch?
If set is active then the Q output will be forced high irrespective of the value of reset.
21. Draw the circuit diagram for an RS latch using only two NAND gates. Are set and
reset asserted low or asserted high?
Asserted low.
22. Draw the schematic for a positive edge triggered master slave D flip-flop using
inverters and transmission gates.
23. What are the functions of the two transmission gates in a transmission gate D latch?
One transmission gate either stops or allows new data to enter the latch. The other
transmission gate provides a feedback path for maintaining the stored value.
24. Draw the schematic of an enable D latch using only transmission gates and inverters
(hint: the input mux can be made using transmission gates)
25. How do you turn on an NMOS transistor strongly?
Apply a gate to source voltage of approximately two or more volts (i.e. gate to source
voltage should be significantly greater that the threshold voltage).
26. How do you make a CMOS transmission gate?
Connect a PMOS and NMOS transistor back to back (i.e. connect their sources and drains
together).
27. Which are better at conducting logic low signals, PMOS or NMOS?
NMOS. They are turned on strong when the drain and source are at logic low (typically 0
volts).
28. Why is CMOS technology better than other technologies?
It offers good performance and generally lower power dissipation. More importantly, it
offers very high levels of integration (i.e. you can put a lot of transistors on a chip).
29. What type of transistors do the common logic families use?
CMOS – PMOS and NMOS, TTL (NPN and PNP), BICMOS (PMOS, NMOS, NPN, and
PNP), ECL (NPN and PNP).
30. Draw and label the characteristic curves for an NMOS transistor.
31. What is the typical threshold voltage of a PMOS transistor? What does this mean?
-1 V. The gate voltage must be at least one volt less than the source voltage to turn on
the transistor.
32. Draw the transistor schematic for a CMOS 3-input NOR gate.
33. Draw the transistor schematic for a complex CMOS gate that implements the function
!F = (A + B) * (C + D). Where ! means inversion.
34. What is the advantage of using both PMOS and NMOS transistors in a CMOS gate.
There is no DC power dissipation (i.e. no continuous current).
35. An NMOS transistor has a load resistor connect to ground. It the transistor source is
connected to ground and a gate voltage is applied to turn on the transistor, what
output voltage and current do you expect?
The output voltage and current are both 0.
36. If you decrease the load resistance, what do you expect to happen to a CMOS gate
output?
The output current will be increased and the output voltages will be farther away from the
supply voltages.
37. If a CMOS gate with a logic low output can provide 10 mA of current at 0.25V, how
much current can it provide when the output is 1V?
It depends on the transistor characteristics, but it would be less than 40 mA due to the
non-linear characteristics of the transistors at high current levels.
38. If a bipolar NPN transistor has the following characteristics: IB = 10uA, VE = 0.3V
and VC = 3V what mode is it operating in? Why?
Linear mode. Transistor is turned on because there is base current. In linear mode
because collector to emitter voltage (2.7V) is greater than the saturation voltage.
39. Draw and label the family of curves for an NPN transistor. Indicate where the
saturation region is.
40. For and NPN transistor, what is the relationship between IB and IC in the saturation
region?
41. What is thepurpose of a Schottky transistor in a TTL circuit?
It is used to prevent a bipolar transistor from going into saturation and thereby reducing
the switching (turn-off) time of the circuit.
42. What is the relationship between IB and IC of a Schottky transistor in saturaion?
A Schottky transistor can’t go into saturation.
43. What is the advantage of a BICMOS gate compared to a CMOS gate?
A BICMOS gate can have larger ouput currents and faster switching if it used bipolar
transistors at the output?
44. Why does a logic low TTL output not go all the way down to 0 volts?
The Schottky transistor at the output will only pull the output voltage down to
approximately 0.3-0.4 Volts.
45. Draw the circuit diagram for a Schottky TTL inverter. Indicate the voltage levels at
each node for a logic high (3V) input.
46. What gives ECL circuits their high speed?
- small voltage swing with differential signals
- common collector (emitter follower) configuration
47. For TTL and CMOS, what logic level would the following voltages be recognized as?
0.5V, 1V, 3V, 4V
0.5V
1V
3V
4V
CMOS
TTL
“0”
“0”
-“1”
“0”
-“1”
“1”
48. What does VIL mean?
The maximum voltage that can be recognized as a logic low input.
49. If a circuit has VIL = 1V, VIH = 4V, VOL = 0.5V, VOH = 3.5V what are the lower and
upper noise margins? Is this a good circuit?
Upper noise margin is –0.5V, lower noise margin is 0.5V. Bad circuit with negative
noise margin (i.e. a valid high output may not be recognized as a valid high input even
without any noise)
50. Why is it important to know both VOH and IOH?
The VOH level is only valid if the output current is less than or equal to the IOH level.