Glacier Journal Of Scientific Research
ISSN :2349-8498
High performance low leakage CMOS multiplier
using 65nm technology
Sona Rani
Deptt.of Electronics and Communication
Yadavindra College of Engineering
Talwandi Sabo, India
sonarani25@gmail.com
Abstract—Multiplication is an important fundamental function
in arithmetic operation. In this paper we present different
types of 8-bit multiplier name as Braun multiplier, Wallace
tree multiplier, Row bypass Braun multiplier, Column bypass
Braun multiplier, Row and Column bypass Braun multiplier
with and without control signal. All these multipliers are
compared in terms of delay, power dissipation, power delay
product and leakage power. These multipliers are simulated
using Tanner v13.0 at 1GHz frequency with 65nm technology
with a supply voltage 1.0v. Simulation results show that the
Braun multiplier with control signal using bridge style adder
has minimum power delay product and Wallace tree multiplier
with control signal has least leakage power.
Candy Goyal
Deptt.of Electronics and Communication
Yadavindra College of Engineering
Talwandi Sabo, India
candygoyal@gmail.com
partial products for each output bit. The logical
circuit diagram of bridge style full adder [4] is
Keywords:- VLSI, CMOS, PDP, multiplier
I. INTRODUCTION
Multipliers play an important role in today’s digital
signal processing and various other applications.
Multipliers are responsible for slowed speed and
consume considerable power. Hence, it is very
important for modern DSP systems to develop lowpower multipliers to reduce the power dissipation and
improve
performance.
Therefore
low-power
multiplier design has been an important part in
modern VLSI system design [1]. In modern VLSI
circuits, low-power and high-speed are the two
parameters which must be considered. Also these low
power design systems reduce cooling cost and
increase the reliability of systems. The increasing
demand for low-power VLSI can be addressed at
different design levels, such as the architectural,
circuit, layout, and the process technology level.
There is always a trade-off between the various
design parameters such as speed, power
consumption, and area [2].
There are different multiplier structures which can be
classified as Serial Multipliers, Parallel multipliers,
Array multipliers, Tree multipliers and so on [3]. A
number of approaches have been adopted to
implement a multiplier circuit with low transistor
count, low power consumption, high speed response
etc. The basic and typical array multiplier performs
multiplication by arranging the full-adders to add the
Fig. 1 Bridge style Full adder
The power consumption of a CMOS transistor can be
divided into three different components: dynamic,
static and short circuit power consumption [5].
Dynamic and short circuit power are also collectively
known as switching power. Leakage or static power
is consumed merely because the circuit is “poweredon”. Switching power is consumed when signals
through CMOS circuits change their logic state,
resulting in the charging and discharging of load
capacitors. Leakage power is primarily due to the
sub-threshold currents and reverse biased diodes in a
CMOS transistor. Thus,
Ptotal= Pdynamic +Pshort_circuit +Pleakage
= V2dd.fclk.CL.α + α/12 (Vdd – 2Vth)3 tr/tf +
IleakageVdd
Where fclk is the system clock frequency, CL is the
load capacitance, α is the switching activity factor, tr/,
tf is the rise and fall time of input signal, Ileakage is the
total leakage current flowing through the device [6].
1
Glacier Journal Of Scientific Research
ISSN :2349-8498
As technologies scaled down leakage power is
increased as compare to dynamic power [7]. Leakage
power dissipation is divided in two major parts, the
sub-threshold leakage and the gate-oxide leakage.
The sub-threshold leakage is caused by short channel
effects and low threshold voltage (Vth), while the
gate-oxide leakage is exponentially increasing with
the decreasing oxide thickness. As in each new
technology the supply voltage decreases to improve
performance and dynamic power dissipation, this
requires the threshold voltage being scaled down
also. Unfortunately, sub-threshold leakage currents
increase exponentially with decreasing threshold
voltage [8].
Multiplier with bypassing technique [11] means turn
off some columns or rows or both in the n x n bit
multiplier
whenever
certain
multiplier
or
multiplicand or both bits are zero. In Row bypassing
technique when the multiplier bits are zero then that
particular rows of adders in the basic multiplier array
are disabled during operation to save the switching
power. The Braun multiplier with row bypassing uses
additional tri-state buffers and multiplexers in order
to skip the FA cell in rows of zero bits. In the
multiplier design, each FA is attached by three tristate buffers and two 2-to-1 multiplexers to bypass
the required row as shown in Fig. 2, Fig. 3
respectively. The extra correcting circuits must be
added to correct the multiplication result because the
rightmost FAs in the rows are able to bypass or must
be disable so output is fed to next row.
In this paper we present multiplier names are Array
multiplier, Braun multiplier, Wallace tree multiplier,
Row bypass Braun multiplier, Column bypass Braun
multiplier and Row and column bypass Braun
multiplier with and without control logic. A control
signal is used to control the leakage power
dissipation.
II. TYPES OF CMOS MULTIPLIER
A. Braun multiplier
Braun multiplier is an simple parallel multiplier and
generally known as carry save array multiplier and an
n bit Array multiplier has n x n array of AND gates to
generate partial products, n x (n-2) full adders and n
half adders. It has regular structure. Therefore it is
easy to design the layout. In VLSI designs, it is easy
to design regular structures. This reduces layout
design time. This regular layout is widely needed in
VLSI math co-processors design and DSP chips
design [9].
Fig. 2 Circuit Diagram of Tristate Buffer
B. Wallace tree multiplier
A Wallace multiplier consists of two parts: a Wallace
Tree for reducing and combining the partial products,
and a Final Adder to generate the actual product [10].
In a Wallace multiplier, the number of partial
products generated is the same as in the Array
Multiplier. Thus there are still N2 AND gates
required for an N-bit by N-bit multiplication. The
difference lies in the way the partial products are
added together in the Wallace tree. Wallace tree has a
logarithmic circuit delay and the array multiplier has
linear delay. So delay of Wallace tree multiplier is
near optimal, but layout is irregular. This architecture
is used where speed is the main concern not the
layout regularity.
C. Braun Multiplier with Row Bypassing
Fig. 3 Circuit Diagram of 2:1 Mux
D. Braun Multiplier with Column Bypassing
In column bypassing technique a column can be
disabled if the corresponding bit in the multiplicand
is 0. There are two advantage of this method. First, it
eliminates the extra correcting circuit. Secondly, the
modified FA is simpler than that of used in the row
bypassing multiplier. The modified FA is only
attached by two tri-state buffers and one 2-to-1
multiplexer [12]. So it uses less hardware as compare
to row bypass multiplier.
2
Glacier Journal Of Scientific Research
E. Braun Multiplier
Bypassing
with Row and Column
ISSN :2349-8498
multipliers. Circuit diagram of different multiplier
design are shown in Fig. 7 to Fig. 11.
In Row and Column Bypassing technique the
addition operation in the FA can be bypassed if the
product, aibj, is 0 and the carry bit, ci,j-1, is 0, that is,
as the product, aibj, is 1 or the bit, ci,j-1, is 1, the
addition operation in the (i+1, j) FA can be executed
[13]. The HAs in the first row of CSAs, are also
replaced with the incremental adder, A+1, and it is
only attached by one tri-state buffer and two 2-to-1
multiplexers. The carry bit in the (i+1, j) FA can be
replaced by the AND result of the product, a ibj, and
the bit, ci,j-1, and the (i+1, j) FA, n > j > 1, can be
replaced with the A+B+1 adder and it is attached by
two tri-state buffers and two 2-to-1 multiplexers.
Fig. 6 Circuit Diagram of bridge style one bit full
adder with control signal
Fig. 4 A+1 adder
Fig. 5 A+B+1 adder
III. MULTIPLIER
LEAKAGE POWER
DESIGN
WITH
LOW
In this section, we design multiplier with control
signal in order to reduce leakage power. In this paper,
a full adder cell is composed of some extra footer cell
to make the circuit faster and low power dissipation
[14] as shown in fig. 6. It has the less leakage power
consumption and less power delay product (PDP) as
compared with conventional static adder. Due to the
minimum time delay of sum and carry out, the adder
core greatly progress the overall performance of
Fig. 7 Circuit Diagram of 8-bit Braun multiplier with
control signal
3
Glacier Journal Of Scientific Research
Fig. 8 Circuit Diagram of 8-bitWallace tree multiplier
with control signal
Fig. 9 Circuit Diagram of 8-bit Row Bypass Braun
Multiplier with control signal
ISSN :2349-8498
Fig. 10 Circuit Diagram of 8-bit Column Bypass
Braun multiplier with control signal
Fig. 11 Circuit Diagram of 8-bit Row and Column
Bypass Braun multiplier with control signal
4
Glacier Journal Of Scientific Research
ISSN :2349-8498
IV. ANALYSIS OF MULTIPLIER
Different types of 8-bit multipliers are compared
named as Array multiplier, Braun multiplier, Wallace
tree multiplier, Row bypass Braun multiplier,
Column bypass Braun multiplier and Row and
Column bypass Braun multiplier by using bridge
style one bit adder with and without control signal.
All the simulations are performed at using 65nm
technology, a 1V power supply at frequency of
1GHz. All circuit logic style is designed using
different gate width of NMOS and PMOS and with a
minimum length of 65nm for NMOS and PMOS.
Simulations are performed using HSPICE. All result
of different multipliers are summerised in the form of
table which are described below:Table1: Average
multipliers at 1.0v.
Power
Type of Multiplier
Braun Mul
Wallace Tree Mul
Row Bypassing Braun
Mul
Column Bypassing
Braun Mul
Row And Column
Bypassing Braun Mul
dissipation
of
8-bit
Frequency (1GHz)
Power(mW
Power(m
) without
W) (with
control
control
signal)
signal)
20.905
9.623
20.791
8.695
48.242
23.364
41.888
19.437
52.023
25.153
Table3: Power Delay Product of 8-bit multipliers at
1.0v
Type of Multiplier
Braun Mul
Wallace Tree Mul
Row Bypassing
Braun Mul
Column Bypassing
Braun Mul
Row And Column
Bypassing Braun Mul
Frequency (1GHz)
PDP(pJ)
PDP(pJ)
(without
(without
control
control
signal)
signal)
7.546
5.071
17.547
7.321
19.731
13.224
17.258
7.308
21.485
10.614
Table 4: Transistors Count of 8-bit multipliers
Type of Multiplier
Braun Mul
Wallace Tree Mul
Row Bypassing
Braun Mul
Column Bypassing
Braun Mul
Row And Column
Bypassing Braun Mul
Transistor
Count
without
control
signal
1648
Transistor
Count
with
control
signal
1785
1648
5046
1776
5188
3622
3759
4196
4352
Table2: Delay of 8-bit multipliers at 1.0v.
Frequency (1GHz)
Table5: Leakage power of 8-bit multipliers
Type of Multiplier
0.361
Delay(ns)(
with
control
signal)
0.527
Leakage
Power (mW)
without
control
signal
Wallace Tree Mul
0.844
0.842
Braun Mul
0.16
Leakage
Power(mW
)
with
control
signal
0.07
Wallace Tree Mul
0.15
0.06
Row Bypassing
Braun Mul
0.409
0.566
35.94
3.41
Column Bypassing
Braun Mul
0.412
0.376
17.92
3.32
Row And Column
Bypassing Braun
Mul
0.413
0.422
Row Bypassing
Braun Mul
Column Bypassing
Braun Mul
Row And Column
Bypassing Braun
Mul
30.33
32.34
Type of Multiplier
Braun Mul
Delay (ns)
(without
control signal)
5
Glacier Journal Of Scientific Research
ISSN :2349-8498
V. CONCLUSION
25
ColmBypass Braun
Mul
Result shows that the Braun multiplier with control
signal using bridge style adder has 32.80% less PDP
as compared to Braun multiplier without control
signal and it has minimum PDP as compared to the
other multiplier analyzed. Wallace tree multiplier
with control signal has 57.37% less leakage power as
compared to Wallace tree multiplier without control
signal and it dissipate less leakage power among all
the other multiplier analyzed. Power delay products
of Braun multiplier with control signal is 5.07462pJ
at frequency 1GHz. Leakage power of Wallace tree
multiplier is 66.63µW.
Row And Colm
Bypass Braun Mul
REFERENCES
20
Braun Mul
PDP (pJ)
15
Wallace Tree Mul
10
Row Bypass Braun
Mul
5
0
PDP(without
PDP(with
control signal) control signal)
Frequency (1GHz)
Fig.12 Comparison of PDP for different 8 bit
multiplier at 1GHz
40
35
30
25
Braun Mul
20
Wallace Tree Mul
15
Row Bypass Braun
Mul
10
Colm Bypass Braun
Mul
5
Row And Colm
Bypass Braun Mul
0
Leakage
Power(without
control signal)
Leakage
Power(with
control signal)
Fig. 13 Comparison of Leakage Power for different 8
bit multipliers
[1] Bellaouar, A., and Elmasry, M., Low-Power
Digital VLSI Design: Circuits and Systems, Boston,
Massachusetts: Kluwer Academic Publishers, 1995.
[2] J. Rabaey, “Digital Integrated Circuits (A Design
Perspective)”, Prentice-Hall, Englewood Cliffs, NJ,
1996.
[3] Neil Weste, A. Eshragian, "Principal of CMOS
VLSI: system perceptive", Pearson/Addision Wesley
publisher, 2005.
[4] Mohammad Reza Bagheri, "Ultra Low Power
Sub-threshold Bridge Style Adder in Nanometer
Technologies", Canadian Journal on Electrical and
Electronics Engineering Vol. 2, No. 7, 2011.
[5] P.R.Panda, “Basic low power digital design”
springer science and business media, 2010.
[6] Sung-Mo Kang, Yusuf Leblebici., "CMOS Digital
Integrated Circuits" Tata McGraw-Hill, 2003
[7] D. Kudithipudi, P. Nair and E. John, "On
Estimation and Optimization of Leakage Power in
CMOS Multipliers", Published in: Circuits and
Systems, 50th Midwest Symposium on , ISSN :15483746, pp 859 - 862,IEEE,2007
[8] Dimitris Bekiaris, George Economakos and
Kiamal Pekmestzi, "A Mixed Style Multiplier
Architecture for Low Dynamic and Leakage Power
Dissipation", Published in:VLSI Design Automation
and
Test
(VLSI-DAT),
2010
International
Symposium on pp.258 - 261, IEEE ,2010.
[9] Anitha R, Alekhya Nelapati, "Comparative Study
of High performance Braun’s
Multiplier using
FPGAs ", IOSR Journal of Electronics and
Communication Engineering (IOSRJECE) ISSN:
2278-2834, Vol no.1, PP 33-37, Issue 4, 2012.
[10] C.S. Wallace, "A suggestion for a fast
multiplier", in IEEE Trans. On Electronic Computers,
vol. EC-13, pp. 14-17, 1964.
6
Glacier Journal Of Scientific Research
ISSN :2349-8498
[11] Sunjoo Hong, Taehwan Roh, and Hoi-Jun Yoo,
"A 145w 8×8 parallel multiplier based on optimized
bypassing architecture", department of electrical
engineering, korea advanced institute of science and
technology (KAIST), daejeon, republic of korea,
IEEE, pp.1175-1178, 2011.
[12] Francis, T. Joseph, T. ; Antony, J.K. "Modified
MAC unit for low power high speed DSP application
using multiplier with bypassing technique and
optimized adders", Computing, Communications and
Networking Technologies (ICCCNT), 4th ICCCNT,
Tiruchengode, India, ISBN:978-1-4799-3925-1, pp 14,IEEE, 2013.
[13] Jin-Tai Yan and Zhi-Wei Chen, "Low-power
multiplier design with row and column bypassing",
department of computer science and information
engineering, chung-hua university, hsinchu, taiwan,
R.O.C, IEEE, pp.227-230, 2009.
[14] Preetisudha Meher, Kamala Kanta Mahapatra,
"Low Power Noise Tolerant Domino1-Bit Full
Adder",
Advances
in
Energy
Conversion
Technologies (ICAECT), ISBN:978-1-4799-2205-5,
pp 125 - 129, IEEE, 2014.
.
7