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JANUSZ A. STARZYK VITA Friday, February 12, 2016 ADDRESSES Electrical Engineering Ohio University Athens, OH 45701 (740)593-1580 html: http://www.ent.ohiou.edu/~starzyk/ Home: 352 Carroll Rd. Athens, OH 45701 (740)593-7675 email: starzyk@bobcat.ent.ohiou.edu EDUCATION M.Sc. in Applied Mathematics in Electrical Engineering, Warsaw University of Technology, Warsaw, Poland, 1971. Ph.D. in Electrical Engineering, Warsaw University of Technology, Warsaw, Poland, 1976. Postdoctoral Fellow, Mc Master University, Hamilton, Canada, 1981-1982. PROFESSIONAL EXPERIENCE OHIO UNIVERSITY - Department of Electrical and Computer Engineering 1983 – present: Professor of Electrical and Computer Engineering. Have supervised more than 40 MSc and 15 PhD students. Current research projects: Self Organizing Learning Array: Involves 1 PhD and 1 MS students. Described on the web page: http://www.ent.ohiou.edu/~webcad/Current_Projects/solar/index.html Machine Intelligence: Involves 2PhD and 2 MS students. WARSAW UNIVERSITY OF TECHNOLOGY -Institute of Electronics Fundamentals 1977-1981: Assistant Professor Visiting Positions: UNIVERSITY OF FLORENCE, MCMASTER UNIVERSITY, NATIONAL INSTITUTE FOR STANDARDS AND TECHNOLOGY, ATT BELL LABORATORIES, WRIGHT LABORATORIES, SARNOFF RESEARCH Consultant for: MAGNOLIA BROADBAND, SARNOFF RESEARCH, WRIGHT LABORATORIES, REDSTONE ARSENAL, ATT BELL LABORATORIES, MAGNETEK, NATIONAL INSTITUTE FOR STANDARDS AND TECHNOLOGY, SVERDRUP TECHNOLOGIES TEACHING INTERESTS Courses in Digital Design, Analog and Digital VLSI, Computer Aided Analysis, Digital Test and Testable Design, VHDL Hardware Description Language with FPGA Design, Machine Intelligence, General electrical engineering. RESEARCH INTERESTS Computational Intelligence, Self Organizing Learning Machines, Neural Networks, Automatic Target Recognition, VLSI and VHDL Systems Design, Dynamically Reconfigurable Design, Analog and Digital Testing, Computer-Aided Design. PUBLICATIONS Over 160 Refereed Journal and Conference Papers Chapters in books 1. "Introduction to Computer Design and Analysis of Electronic Networks", (Co-author), Wydawnictwa PW, Warszawa, 1978 (in Polish). 2. Co-author of Polish translation "Computer-aided analysis of electronic circuits, algorithms and computational techniques", by L.O. Chua and P.M. Lin, Wydawnictwa Naukowo-Techniczne, Warszawa, 1981. 3. "Advances in Circuits and Systems - Selected Papers on Analog Fault Diagnosis", (coauthor), IEEE Press, New York 1987. 4. "Analog Methods for Circuit Analysis and Diagnosis", (Co-author), Marcel Dekker, Inc., New York, 1988. Recent Journal Papers 1. H. He and J. A. Starzyk, "A Self-Organizing Learning Array System for Power Quality Classification Based on Wavelet Transform", IEEE Trans on Power Delivery, vol. 21, No. 1, Jan 2006. 2. J. A. Starzyk, Y. Guo, and Z. Zhu, “Dynamically reconfigurable neuron architecture for the implementation of self-organising learning array” Int. J. Embedded Systems, vol. 2, Nos. 1/2, 2006. 3. J. A. Starzyk, and H. He, “Anticipation-Based Temporal Sequences Learning in Hierarchical Structure” IEEE Trans. on Neural Networks, 2006 (to appear). 4. J. A. Starzyk and H. He, “A Novel Low Power Logic Circuit Design Scheme,” IEEE Trans. Circuits Syst. II, 2006. (to appear) 5. J. A. Starzyk, Z. Zhu, and Y. Li, „Associative Learning in Hierarchical Self Organizing Learning Arrays“ IEEE Trans. on Neural Networks, 2006 (to appear) 6. Z. Zhu, H. He, J.A. Starzyk, and C. Tseng “Self-Organizing Learning Array and its Application to Economic and Financial Problems” Elsevier Science, 24 May 2006. 7. J. A. Starzyk, Z. Zhu and T.-H. Liu "Self-Organizing Learning Array" IEEE Trans. on Neural Networks, vol. 16, no. 2, pp. 355-363, March 2005. 8. J. A. Starzyk and F. Wang, "Dynamic Probability Estimator for Machine Learning" IEEE Trans. on Neural Networks, vol.15, no 2, March 2004, pp.298-308. 9. J. A. Starzyk, Mohn, R.P. and Jing, L., "A Cost-Effective Approach to the Design and Layout of a 14-b Current-Steering DAC Macrocell", IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, Vol. 51 , no. 1 , Jan. 2004, pp. 196 200. 10. J. A. Starzyk, Dong Liu, Zhi-Hong Liu, D. Nelson and J. Rutkowski, “Entropy-based optimum test points selection for analog fault dictionary techniques,” IEEE Transactions on Instrumentation and Measurement, vol. 53, no. 3, June 2004, pp. 754-761. 11. J. Pang, F. Van Graas, J. Starzyk, and Z. Zhu, "Fast Direct GPS P-Code Acquisition" GPS Solutions, Springer Verlag, Volume 7(3), 2003, pp.168-175. 12. D. E. Nelson, J. A. Starzyk, and D. D. Ensley, "Iterated Wavelet Transformation and Signal Discrimination for HRR Radar Target Recognition," IEEE Trans. Systems Man and Cybernetics. Vol. 33, no.1, Jan. 2003, pp.52-57. 13. D. Liu and J. A. Starzyk, " A generalized fault diagnosis in dynamic analog circuits" Int. Journal of Circuit Theory and Applications, vol. 30, pp. 487-510, 2002. 14. D. E. Nelson, J. A. Starzyk, and D. D. Ensley, "Iterative Wavelet Transformation and Signal Discrimination for HRR Radar Target Recognition," Multidimensional Systems and Signal Processing, Vol. 14 No.2. 2002. 15. J. Becker, A. Alsolaim, M. Glesner, and J. Starzyk, “A Parallel Dynamically Reconfigurable Architecture for Flexible Aplication-Tailored Hardware/Software Systems in Future Mobile Communication”, The Journal of Supercomputing, Erratum Vol. 23, 132, 2002, 19(1): 105-127 (2001). 16. J. Pang and J. A. Starzyk, "Fault Diagnosis in Mixed-Signal Low Testability System" An International Journal of Analog Integrated Circuits and Signal Processing, vol. 28, no.2, August 2001, pp. 159-170. 17. J. A. Starzyk and Y.-W. Jan, and F. Qiu, "A DC-DC Charge Pump Based on Voltage Doublers", IEEE Trans. Circuits and Systems, Part I, vol. 48, no. 3, March 2001, pp. 350359. 18. G. N. Stenbakken, D. Liu J. A. Starzyk, and B. C. Waltrip, "Nonrandom Quatization Errors in Timebases", IEEE Trans. on Instrumentation and Measurement, vol. 50, no. 4, Aug. 2001, pp.888-892. 19. J. A. Starzyk, D. E. Nelson, and K. Sturtz, " A Mathematical Foundation for Improved Reduct Generation in Information Systems", Journal of Knowledge and Information Systems, v. 2 n. 2, March 2000 p.131-146. 20. J. A. Starzyk, J. Pang, S. Manetti, G. Fedi, and C. Piccirilli, "Finding Ambiguity Groups in Low Testability Analog Circuits", IEEE Trans. Circuits and Systems, Part I, vol 47, no. 8, 2000, pp. 1125-1137. 21. G. Fedi, S. Manetti, J. A. Starzyk, M. C. Piccirilli "Determination of an Optimum Set of Testable Components in the Fault Diagnosis of Analog Circuits", IEEE Trans. Circuits and Systems, Part I, vol. 46, no.7, 1999, 779-787. 22. J. A. Starzyk, D. E. Nelson, and K. Sturtz, "Reduct Generation in Information Systems", Bulletin of International Rough Set Society, 1999, 3 (1/2). Other Journal Papers 1. J. A. Starzyk, "Topological Methods of Analysis of LSL Networks with Nullators and Norators", Prace Naukowe PW, Elektronika, No. 20, Warszawa, 1975, (in Polish), pp. 73-89. 2. J. A. Starzyk, "Topological, Analysis of LSL Networks with Nullators and Norators; Impedance Dependencies", Prace Naukowe PW, Elektronika, No. 20, Warszawa, 1975, (in Polish), pp. 61-71. 3. J. A. Starzyk, "Complement of Columns of Constant-row Structural Number to the Factorizable Number", Arch. Elektrot., z.2, 1975 (in Polish), pp. 237-244. 4. A. Konczykowska and J. A. Starzyk "Determination of Structural Number of a Partitioned Graph. Part I and II.", Arch. Elektrot z.2, 1975, (in Polish), pp. 245-262. 5. J. A. Starzyk, "Topological Synthesis of Linear Active Networks Described by Multivariable Functions", Arch. Elektrot., z.2, 1976, (in Polish), pp. 287-295. 6. J. A. Starzyk, "New Method for Designing Complete Trees of a Pair of Conjugate Graphs", Arch. Elektrot., z.1, 1977, (in Polish), pp. 41-46. 7. J. A. Starzyk, "Application of the Controlled Expansions Method to the Topological Analysis of Circuits", Arch. Elektrot., z.1, 1977, (in Polish), pp. 47-58. 8. J. A. Starzyk, "Determination of the Nullator-Norator Graph's Complete Trees", Radio Electronics and Communication Systems, t.XX 12, 1977, (in Russian), pp. 9-15. 9. J. A. Starzyk, and J. Wojciechowski, "Topological Analysis and Synthesis of Electrical Networks by the Method of Structural Numbers", Raport Naukowy IPE, Warszawa, 1977, (in Polish). 10. J. A. Starzyk, "Generation of Complete Trees by the Method of Modified Structural Matrix", Arch. Elektrot., z.4, 1978, (in Polish), pp. 843-852. 11. J. A. Starzyk, "Signal Flow-Graph Analysis by Decomposition Method", IEE Proc. on Electronic Circuits and Systems, No. 2, April 1980, pp. 81-86. 12. G. Centkowski and J. A. Starzyk, "Topological Synthesis of LLF Networks", Acta Polytechnica, CVUT, Praha, 1980, pp. 77-86. 13. J. A. Starzyk and E. Sliwa, "Hierarchic Decomposition Method for the Topologitronic Networks", Int. Journal of Circuit Theory and Applications, Vol. 8, 1980, pp. 407-417. 14. J. A. Starzyk, "Topological Analysis of Large Electronic Circuits", Prace Naukowe, Elektronika, No. 55, WPW, Warszawa, 1981, (in Polish), 184 pp. 15. J. A. Starzyk, "An Efficient Cluster Algorithm", Acta Polytechnica, CVUT, Praha, 1981, pp. 49-55. 16. J. A. Starzyk and J. W. Bandler, "Multiport Approach to Multiple-Fault Location in Analog Circuits", IEEE Trans. on Circuits and Systems, vol. CAS-30, 1983, pp. 762-765. 17. J. A. Starzyk and E. Sliwa, "Upward Topological Analysis of Large Circuits Using Directed Graph Representation", IEEE Trans. on Circuits and Systems, vol. CAS-31, 1984, pp. 410-414. 18. A. E. Salama, J. A. Starzyk and J. W. Bandler, "A Unified Decomposition Approach for Fault Location in Large Analog Circuits", IEEE Trans. on Circuits and Systems, vol. CAS-31, 1984, pp. 609-622. 19. J. A. Starzyk, R. M. Biernacki and J. W. Bandler, "Evaluation of Faulty Elements within Linear Subnetworks", Int. Journal of Circuit Theory and Applications, vol. 12, 1984, pp. 23-37. 20. J. A. Starzyk and A. Konczykowska, "Flowgraph Analysis of Large Electronic Networks", IEEE Trans. on Circuits and Systems, vol. CAS-33, 1986. 21. G. N. Stenbakken and J. A. Starzyk, "Diakoptic and Large Change Sensitivity Analysis", IEE Proc. G, Circuits, Devices and Systems, vol. 139, no.1, 1992, pp.114-118. 22. J. A. Starzyk and H. Dai, "A Decomposition Approach for Testing Large Analog Networks," Journal of Electronic Testing - Theory and Applications, no.3, 1992, pp. 181195. 23. J. A. Starzyk and X. Fang, "A CMOS Current Mode Winner-Take-All Circuit with both Excitatory and Inhibitory Feedback", Electronics Letters, vol.29, no.15, 1993, pp. 908910. 24. J. A. Starzyk, "Hierarchical Analysis of High Frequency Interconnect Networks", IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol.13, no.5, 1994, pp. 658-664. Recent Conference Papers 1. J.A.Starzyk, Yinyin Liu, and Haibo He, “Challenges of Embodied Intelligence”, Proc. Int. Conf. on Signals and Electronic Systems, ICSES'06, Lodz, Poland, Sep. 17-20, 2006. 2. S. Kaya, H. Hamed and J. A. Starzyk, “Low-Power Tuneable Analog Circuit Blocks Based on Nanoscale Dual-Gate MOSFETs”, 6th IEEE Conf. on Nanotechnology – IEEE Nano 2006, 16-20 July, 2006, Cincinnati, OH, USA. 3. S. Kaya, H. Hamed and J. A. Starzyk, “Compact Tunable Current-Mode Analog Circuits Using DGMOSFETs”, IEEE Int. SOI Conf. Oct. 2 – 5, 2006, Niagara Falls, NY. 4. J. A. Starzyk, Z. Zhu, and Y. Li, "Associative Learning in Hierarchical Self Organizing Learning Arrays", Proc Int. Conf. Artificial Neural Networks, Warsaw, Poland, Sep. 1115, 2005. 5. Janusz A. Starzyk, and Yue Li, David D. Vogel, "Neural Network with Memory and Cognitive Functions", Proc Int. Conf. Artificial Neural Networks, Warsaw, Poland, Sep. 11-15, 2005. 6. J.A.Starzyk, Mingwei Ding, Haibo He, "Optimized Interconnections in Probabilistic SelfOrganizing Learning", Proc. IASTED Int. Conf. on Artificial Intelligence and Applications, Innsbruck, Austria, Feb. 14-16, 2005. 7. J. A. Starzyk,Y. Guo, and Z. Zhu, ”Dynamically Reconfigurable Neuron Architecture for the Implementation of Self-Organizing Learning Array”, Proc. 18th Int. Parallel and Distributed Processing Symposium, Santa Fe, New Mexico, April 26– 30, 2004. 8. H. He, J. A. Starzyk, "DesignPower Quality Disturbances Analysis based on Wavelet Multiresolution Decomposition", American Mathematical Society (AMS) Conf., Ohio University, Athens, OH, March 26-27, 2004. 9. J. A. Starzyk, Y. Guo, Z. Zhu, “SOLAR and its hardware development", Proc. Computational Intelligence and Natural Computing, 2003 (CINC’03), 2003, Cary, North Carolina USA , Sept. 26-30, 2003. 10. J. A. Starzyk, Zhen Zhu, H. He and Zhineng Zhu, "Self-Organizing Learning Array and Its Application to Economic and Financial Problems, "Proc. Joint Conference on Information Systems, 2003, Cary, North Carolina USA, Sept. 26-30, 2003. 11. J. A. Starzyk and T.-H. Liu, “Design of a Self-Organizing Learning Array System”, Proc. IEEE Int. Symposium on Circuits and Systems, May 26-29, Bangkok, Thailand, 2003. 12. J. A. Starzyk and R. Mohn, “Cost-Oriented Design of a 14-bit Current Steering DAC Macrocell”, Proc. IEEE Int. Symposium on Circuits and Systems, May 26-29, Bangkok, Thailand, 2003. 13. J. Pang and J.A. Starzyk, ”Fast Direct GPS Signal Acquisition Using FPGA”, Proc. (Krakow, Poland, 2003). 14. J. A. Starzyk, and Y. Guo, “A Self-Organizing Learning Array and its HardwareSoftware Co-Simulation”, Proc. ECCTD, (Krakow, Poland, 2003). 15. Alaqeeli, J. A. Starzyk, F. van Graas, “Real Time Acquisition and Tracking for GPS Receiver”, Proc. IEEE Int. Symposium on Circuits and Systems, May 26-29, Bangkok, Thailand, 2003. 16. J. A. Starzyk, and Y. Guo, “Dynamically Self-Reconfigurable Machine Learning Structure for FPGA Implementation” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) Las Vegas, Nevada, USA, June 23 - 26, 2003. 17. J. A. Starzyk and D. Liu, "A Decomposition Method for Analog Fault Location", IEEE Int. Symposium on Circuits and Systems, May 26-29, Scottsdale, Arizona, 2002. 18. J. A. Starzyk and D. Liu, "Locating Stuck-at Faults in Analog Circuits", IEEE Int. Symposium on Circuits and Systems, May 26-29, Scottsdale, Arizona, 2002. 19. J. Starzyk and Z. Zhu, "Software Simulation of a Self-Organizing Learning Array System", The 6th IASTED Int. Conf. Artificial Intelligence & Soft Comp.(ASC 2002), July 17-19, 2002, Banff, Alberta, Canada. 20. J. Pang, J. A. Starzyk, "P-code Generator FPGA Design for Direct GPS P(Y)-Code Acquisition", 12th International Conference on Field Programmable Logic and Applications (FPLA), 2002. 21. M. Ding, A. Alsolaim, and J. Starzyk, "Designing and Mapping of a Turbo Decoder for 3G Mobile Systems Using Dynamically Reconfigurable Architecture " Engineering of Reconfigurable Systems and Algorithms, ERSA'02, The Int. Multi Conference in Computer Science, June 24-27, Las Vegas, Nevada, 2002. 22. J. A. Starzyk Y. Guo, "A Self Organized Classifier Based on Maximum Information Index and its Develpoment Using VHDL", 2002 IEEE Int. Symposium on Intelligent Signal Processing and Communication Systems, 21-24 November 2002, Kaohsiung, Taiwan, R.O.C. 2002. 23. J.A. Starzyk and D. Liu, "A new approach to multiple fault diagnosis in linear analog circuits," Proceeding of the 7th IEEE International Mixed Signal Testing Workshop (IMSTW), Atlanta, GA, Jun. 2001. 24. J. A. Starzyk* and D. Liu, "A Method for Multiple Fault Diagnosis in Analog Circuits" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001). 25. J. A. Starzyk and L. Jing, "Analog Circuits for Self Organizing Neural Networks Based on Mutual Information" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001). 26. Y. Zeng and J. A. Starzyk, "Statistical Approach for Clustering in Pattern Recognition" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001). 27. Alaqeeli and J. A. Starzyk, "Hardware Implementation of Fast Convolution for GPS Signal Acquisition Using FPGA" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001). 28. A.Alsolaim and J. A. Starzyk, "Dynamically Reconfigurable Solution in the Digital Baseband Processing for Future Mobile Radio Devices" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001). 29. D. E. Nelson and J. A. Starzyk, "High Range Resolution Radar Signal Classification: A Partitioned Rough Set Approach" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001). 30. J. A. Starzyk and Y. Guo, "An Entropy-based Learning Hardware Organization Using FPGA" Proc. Southeastern Symposium on System Theory, (Athens, OH, 2001). 31. J. A. Starzyk and D. Liu, "Multiple Fault Diagnosis of Analog Circuits Based on Large Change Sensitivity Analysis" Proc. ECCTD, (Espoo, Finland, Aug. 2001). 32. D. E. Nelson and J. A. Starzyk, "High Range Resolution Radar - Extensions to Rough Set Theory for Automatic Target Recognition", SPIE 15th Annual Int. Symp. on Aerospace/Defense Sensing Simulation and Controls, (Orlando FL, April 2001) Best Paper award. 33. J. A. Starzyk and D. Liu, "Multiple Fault Diagnosis of Analog Circuits by Locating Ambiguity Groups in Test Equation", Proc. IEEE Int. Symp. Circuits and Systems (Sydney, Australia, 2001). 34. J. A. Starzyk and Z. Zhu, "Averaging Correlation for C/A Code Acquisition and Tracking in Frequency Domain", Proc. Midwest Symp. on Circuits and Systems (Dayton, OH, Aug. 2001). 35. J. A. Starzyk and Y. Guo, "Reconfigurable Self-Organizing NN Design Using Virtex FPGA", Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (Las Vegas, NV, June 2001). 36. X. S. Song and J. A. Starzyk, "Feature Selection using Mutual Information and Statistical Techniques", Proc. 2001 IEEE Military Communications Conf. (MILCOM’2001), Washington D.C, October 2001. 37. Alsolaim, J. Becker, M. Glesner, and J. Starzyk, "A Dynamically Reconfigurable System-on-a chip Architecture for Future Mobile Digital Signal Processing", The European Signal Processing Conference EUSIPCO, (Sept. 5 - 8, 2000, Tampere, Finland). 38. J. Becker, M. Glesner, A. Alsolaim, J. Starzyk, "Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures", the 2000 Int. Conf. on Parallel and Distributed Processing Techniques and Apllications, (Las Vegas, NV, June 2000). 39. Alsolaim, J. Becker, M. Glesner, J. Starzyk. "Dynamically Reconfigurable Array Architecture for Future Mobile Digital Baseband Processing." 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), April 16-19, 2000, Napa Valley, California. 40. Y. Zeng and J. Starzyk, "Piecewise Linear Approach: a New Approach in Automatic Target Recognition," SPIE 14th Annual Int. Symp. on Aerospace/Defense Sensing Simulation and Controls, (Orlando FL, April 2000). 41. J. Starzyk, J. Pang, "Fault Diagnosis in Analog and Mixed Mode Low Testability Systems", Proc. IEEE Int. Symp. Circuits and Systems (Geneva, Switzerland, 2000). 42. D. E. Nelson and J. A. Starzyk "Fusing Marginal Reducts for HRR Target Identification" 4th World Multi-Conference on Systems, Cybernetics and Informatics (SCI2000), (Orlando, Florida, July 2000), pp. 452-460 Best Paper award. 43. G. N. Stenbakken, D. Liu J. Starzyk, and B. C. Waltrip, "Nonrandom Quatization Errors in Timebases", Proc. IEEE Instrumentation and Measurement Technology Conference (Baltimore, MD May 2000). 44. J. Starzyk and J. Pang, "Evolvable Binary Artificial Neural Network for Data Classification", the 2000 Int. Conf. on Parallel and Distributed Processing Techniques and Apllications, (Las Vegas, NV, June 2000). 45. F. Qiu, J. A. Starzyk and Y.-W. Jan, "Analog VLSI Design of Multi-phase Voltage Doublers with Frequency Regulation", the 1999 Southwest Symposium on Mixed-Signal Design, (Tucson, AZ, April, 1999). 46. J. A. Starzyk and Y.-W. Jan," A Simulation Program Emphasized on DC Analysis of VLSI Circuits: SAMOC", the 1999 Southwest Symposium on Mixed-Signal Design, (Tucson, AZ, April, 1999). 47. G. N. Stenbakken, D. Liu, J. A. Starzyk and B. C. Waltrip, "A new method to compensate quantized time-base nonlinearity of sampling instruments," Workshop on Software Embedded Systems Testing (WSEST), National Institute of Standards and Technology, Gaithersburg, MD, Nov. 1999. 48. V. Brygilevicz, J. Wojciechowski, and J. A. Starzyk, "Testing of Analog Dynamic Systems Based on Integral Sensisitivity", Proc. ECCTD, (Stresa, Italy, Aug. 1999). 49. J.A. Starzyk, J. Pang, G. Fedi, R. Giomi, S. Manetti, "A Software Program for Ambiguity Group Determination in Low Testability Analog Circuits", Proc. ECCTD, (Stresa, Italy, Aug. 1999). Other Conference Papers and Presentations 50. J. A. Starzyk, "Complement of Set of Trees", Eight Asilomar Conf. Circuits, Systems and Computers, (Pacific Grove), 1974, pp. 227-230. 51. J. A. Starzyk, "Problems in Topological Analysis", First National Conf. URSI (Warsaw, 1975), (in Polish), pp. 250-252. 52. J. A. Starzyk, "Topological Synthesis of Multivariable Network Functions", Third Int. Symp. on Network Theory (Split, 1975), pp. 555-564. 53. J. A. Starzyk, "Edge Orientation in Topological Synthesis of Linear Networks", Fifth Symp. Mathematical Methods in Electrical Engineering, (Podlesice, 1976), (in Polish), pp. 169-179. 54. J. A. Starzyk, "Selected Topics in Topological Synthesis of Networks by the Method of Structural Numbers", Symp. for XXV Anniversary of Electrical Engineering Dept. (Warsaw, 1976), (in Polish), pp. 116-117. 55. J. A. Starzyk, "Topological Synthesis of Linear Active Networks with the Method of Structural Numbers", Proc. European Conf. Circuit Theory and Design (Genova, 1976), pp. 340-348. 56. J. A. Starzyk, "Topological Synthesis of Linear Network with Grounded Operational Amplifiers", Proc. of 2nd Polish-Czech Workshop on Circuit Theory (Czarlino, 1977), pp. 201-206. 57. J. A. Starzyk, "The Distor Graphs", Proc. of 3rd Czech-Polish Workshop on Circuit Theory (Prenet, 1978). 58. J. A. Starzyk and E. Sliwa, "Topological Analysis by Hierarchic Decomposition Method", Fourth Int. Symp. on Network Theory (Ljubljana, 1979), pp. 155-160. 59. J. A. Starzyk and A. Konczykowska, "Hierarchical Decomposition of Signal-Flow Graphs", Third Int. Conf. Electronic Circuits (Prague, 1979), pp. 248-251. 60. J. A. Starzyk, "Advanced Topological Analysis", Proc. of 4th Polish-Czech Workshop on Circuit Theory (Bocheniec, 1979), pp. 90-94. 61. G. Centkowski, J. A. Starzyk and E. Sliwa, "Computer Imple-mentation of Topological Methods in the Analysis of Large Networks", Proc. European Conf. Circuit Theory and Design (Warsaw, 1980), pp. 69-74. 62. Konczykowska and J. A. Starzyk, "Computer Analysis of Large Signal Flowgraphs by Hierarchical Decomposition Method", Proc. European Conf. Circuit Theory and Design (Warsaw, 1980), pp. 408-413. 63. R. M. Biernacki and J. A. Starzyk, "Sufficient Test Conditions for Parameter Identification of Analog Circuits Based on Voltage Measurements", Proc. European Conf. Circuit Theory and Design (Warsaw, 1980), pp. 233-241. 64. J. A. Starzyk, "An Efficient Cluster Algorithm", Proc. of 5th Czech-Polish Workshop on Circuit Theory (Podbierady, 1980). 65. R. M. Biernacki and J. A. Starzyk, "A Test Generation Algorithm for Parameter Identification of Analog Circuits", Proc. European Conf. Circuit Theory and Design, (The Hague, 1981), pp. 993-997. 66. G. Centkowski, J. A. Starzyk and E. Sliwa, "Symbolic Analysis of Large LLS Networks by Means of Upward Hierarchical Analysis", Proc. European Conf. Circuit Theory and Design (The Hague, 1981), pp. 358-361. 67. Konczykowska and J. A. Starzyk, "Computer Justification of Upward Topological Analysis of Signal-Flow Graphs", Proc. European Conf. Circuit Theory and Design, (The Hague, 1981), pp. 464-467. 68. J. A. Starzyk and J. W. Bandler, "Nodal Approach to Multiple-Fault Location in Analog Circuits", Proc. IEEE Int. Symp. Circuits and Systems (Rome, 1982), pp. 1136-1139. 69. J. W. Bandler, R. M. Biernacki, A. E. Salama and J. A. Starzyk, "Fault Isolation in Linear Analog Circuits Using the Ll Norm", Proc. IEEE Int. Symp. Circuits and Systems (Rome, 1982), pp. 1140-1143. 70. H. Gupta, J. W. Bandler, J. A. Starzyk and J. Sharma, "A Hierarchical Decomposition Approach for Network Analysis", Proc. IEEE Int. Symp. Circuits and Systems (Rome, 1982), pp. 643-646. 71. J. A. Starzyk and J. W. Bandler, "Design of Tests for Parameter Evaluation within Remote Inaccessible Faulty Subnetworks", Proc. IEEE Int. Symp. Circuits and Systems (Newport Beach, CA, 1983), pp. 1106-1109. 72. E. Salama, J. A. Starzyk and J. W. Bandler, "A Unified Decomposition Approach for Fault Location in Large Analog Circuits", Proc. European Conf. Circuit Theory and Design (Stuttgart, 1983). 73. J. A. Starzyk, "Decomposition Approach to a VLSI Symbolic Layout with Mixed Constraints", Proc. IEEE Int. Symp. Circuits and Systems (Montreal, 1984). pp. 457-460. 74. J. A. Starzyk and M. A. El-Gamal, "An Optimization Approach to Fault Location in Analog Circuits", Proc. European Conf. Circuit Theory and Design (Prague, 1985). 75. J. A. Starzyk and V.S.R. Dandu, "Overlapped Multi-Bit Scanning Multiplier", Proc. IE: VLSI in Computers (Port Chester, NY, 1985). 76. J. A. Starzyk and H. Dai, "Element Evaluation in the Resistive Networks", Proc. 28th Midwest Symp. on Circuits and Systems (Louisville, Kentucky, 1985). 77. J. A. Starzyk and S. C. Rastogi, "Hierarchical Decomposition Approach to D.C. Power Flow Solution", Proc. 28th Midwest Symp. on Circuits and Systems (Louisville, Kentucky, 1985). 78. J. A. Starzyk and M. A. El-Gamal, "Topological Conditions for Element Evaluation", Proc. 28th Midwest Symp. on Circuits and Systems (Louisville, Kentucky, 1985). 79. J. A. Starzyk and H. Dai, "Multifrequency Measurement of Testability in Analog Circuits", Proc. IEEE Int. Symp. Circuits and Systems (Philadelphia, PA, 1987). 80. J. A. Starzyk and H. Dai, "Sensitivity Based Testing of Nonlinear Dynamic Circuits", Proc. IEEE Int. Symp. Circuits and Systems (Espoo, Finland, 1988). 81. J. A. Starzyk and M. A. El-Gamal, "Diagnosability of Analog Circuits a Graph Theoretical Approach", Proc. IEEE Int. Symp. Circuits and Systems (Espoo, Finland, 1988). 82. J. A. Starzyk and H. Dai, "Fault Diagnosis and Calibration of Large Analog Circuits", Proc. IEEE Int. Symp. Circuits and Systems (Espoo, Finland, 1988). 83. J. A. Starzyk and M. El-Gamal, "Fault Diagnosis of Nonlinear Resistive Circuits", Proc. 31st Midwest Symp. on Circuits and Systems (St. Louis, MO, 1988). 84. J. A. Starzyk and M. Eshghi, "Highly Parallel Adaptive Filter," Proc. IEEE Int. Symp. Circuits and Systems (Portland, OR, 1989). 85. J. A. Starzyk and E. Sliwa, "Tolerances in Symbolic Network Analysis," Proc. IEEE Int. Symp. Circuits and Systems (Portland, OR, 1989) - invited paper. 86. J. A. Starzyk and H. Dai, "Time Domain Testing of Large Nonlinear Circuits," Proc. European Conf. Circuit Theory and Design, (Brighton, United Kingdom, 1989). 87. J. A. Starzyk and H. Dai, "A Decomposition Approach for Parameter Identification in Large Scale Networks," Proc. IEEE Int. Symp. Circuits and Systems (New Orleans, LA, 1990). 88. J. A. Starzyk and M. El-Gamal, "Artificial Neural Network for Testing Analog Circuits", Proc. IEEE Int. Symp. Circuits and Systems (New Orleans, LA, 1990). 89. J. A. Starzyk and H. Dai, "Automated Testing Using Circuit Decomposition", Proc. IEEE Instr. Measurement Technology Conf. (Atlanta, GA, 1991). 90. J. A. Starzyk and X. Wu, "Approximation Using Linear Fitting Neural Network", Proc. Artificial Neural Networks in Engineering Conf. (St. Louis, MO, 1991). 91. J. A. Starzyk, "Neural Networks in Analog Fault Diagnosis", VII Riunione Annuale Dei Ricercatori, (Trani, Italy, 1991). 92. J. A. Starzyk and C. H. Chen, "A One Dimensional Processor Array for LU Decomposition", Proc. IEEE Int. Workshop on Intelligent Signal Processing and Communication Syst. (Taipei, Taiwan, ROC, 1992). 93. J. A. Starzyk and N. Ansari, "Feedforward Neural Network for Handwritten Character Recognition", Proc. IEEE Int. Symp. Circuits and Systems (San Diego, CA, 1992). 94. J. A. Starzyk and H. Dai, "Noninvasive Voltage Measurement Through an On-Chip Test Structure", Proc. IEEE Int. Test Conference (Baltimore, MD, 1992). 95. J. A. Starzyk and S.K. Chai, "Vector Contour Representation for Object Recognition in Neural Networks", IEEE Int. Conf. Systems, Man, and Cybernetics, (Chicago, IL, 1992). 96. J. A. Starzyk and N. Ansari, "Distance Field Approach to Handwritten Character Recognition", Proc. Fifth Conf. on Neural Networks and Parallel Distributed Processing, (Fort Wayne, IN, 1992). 97. X. Fang and J. Starzyk, "A novel winner-take-all circuit", the World Conf. on Neural Networks, (Portland, OR, 1993). 98. J. A. Starzyk and J. Zou, "On-line error detection in analog and mixed-signal systems", IEEE Int. Test Conference, (Baltimore, MD, 1993). 99. J. A. Starzyk and X. Fang, "System level design of a complex neural network for target recognition", IEEE Int. Conf. on Neural Network Applications to Signal Processing, (Singapore, 1993). 100. J. A. Starzyk and C.-H. Chen, "A VLSI Inner Product Processor with Built-in Self Test for Real Time DSP Applications", Int. Conf. on Signal Proc. Applications and Technology, (Santa Clara, CA, 1993). 101. X. Fang and J. A. Starzyk, "VLSI design of neural network based image processor", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994). 102. J. A. Starzyk and Y-W. Jan, "Algorithm and architecture for feature extraction in image processong", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994). 103. J. A. Starzyk and S. Chai, "Supervised learning with potentials for neural network- based object recognition", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994). 104. J. A. Starzyk and C-H. Chen, "A VLSI inner-product processor for real-time DSP applications", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994). 105. J. A. Starzyk and M. SenthilKumar, "Partial arithmetic - algorithms and architecture", Proc. Southeastern Symposium on System Theory, (Athens, OH, 1994). 106. J. A. Starzyk, Z. H. Liu, and J. Zou, "An organization of the test bus for analog and mixed-signal systems", Proc. of IEEE VLSI Test Symposium, (Cherry Hill, N.J. 1994). 107. J. A. Starzyk and S. Chai, "Object representation using Fourier descriptors in pattern classification", Proc. Artificial Neural Networks in Engineering Conf. (St. Louis, MO, 1995). 108. J. A. Starzyk and Ying-Wei Jan, "Low Power Voltage Based Winner Takes All Circuit for Analog Neural Networks", OAI Neural Network Symposium, (Athens, OH, 1995). 109. J. A. Starzyk and Xingyuan Lee, "Rapid Object Identification Based on Fourier Descriptors", OAI Neural Network Symposium, (Athens, OH, 1995). 110. J. A. Starzyk and J. Zou, "Direct Symbolic Analysis of Analog Networks", Proc. Midwest Symp. on Circuits and Systems (Ames, Iowa, 1996). 111. J. A. Starzyk and Ying-Wei Jan, "A Voltage Based Winner Takes All Circuit for Analog Neural Networks", Proc. Midwest Symp. on Circuits and Systems (Ames, Iowa, 1996). 112. J. A. Starzyk and D. Nelson, "Independent Classifiers in Ontogenic Neural Networks for ATR", Adaptive Distributed Parallel Computing Symposium (Fairborn, OH, 1996). 113. D. E. Nelson and J. A. Starzyk, "Advanced Feature Selection Methodology for Automatic Target Recognition", Proc. Southeastern Symposium on System Theory, (Coolville, TN, 1997). 114. Z-H. Liu and J. A. Starzyk, "Mixed Signal Testing of Analog Components on Printed Circuit Boards", Proc. Midwest Symp. on Circuits and Systems (Sacramento, CA, 1997). 115. R. Morawski, B. Manhire, and J. Starzyk, Engineering Education in Poland", ASEE Conf., Seattle, June, 1998. 116. J. A. Starzyk, D. E. Nelson, and K. Sturtz, "Reduct Generation in Information Systems", The Sixth Int. Workshop on Rough Sets, Data Mining and Granular Computing, at JCIS'98, (Research Triangle Park, NC), Oct. 1998. PATENTS Janusz A. Starzyk, "Dynamic Probability Estimator for Self-Organizing Data-Driven Learning Hardware", Ohio University, Provisional Patent Application, prepared in February 2003. Janusz A. Starzyk, "Self-Organizing Data-Driven Learning Hardware with Local Interconnections", Ohio University, US Patent Application, Serial # 10/174,038, filed on June 18, 2002. Janusz A. Starzyk, Russell Mohn, Thomas Senko, "Algorithm for the Reduction of Systematic Errors in Current Steering DAC", Sarnoff Corp., US Patent Application, Serial No.: 395690, Filed: March 24, 2003. Janusz A. Starzyk and Dale E. Nelson, "Object Identification System and Method", Ohio University, International Patent Application, PCT /US01/22852, Serial # 60/220,768, filed on July 21, 2000. Invited talks (since 1991): Seminar, “Hierarchical Analysis of VLSI Interconnect,” AT&T Bell Labs, Dr. B. Ackland, VLSI Systems Group, 1991. The Keynote Speaker at the VII Riunione Annuale Dei Ricercatori, Trani, Italy, 1991. Seminar, “Neural Networks for Analog Testing and Approximation”, University of Florence, Italy Dr. Liberatore, 1991. Seminar, “Artificial Neural Vision Learning System” Institute of Electronic Systems, Warsaw Technical University, 1992. Seminar, “Hardware Implementation of ANVIL Algorithms”, Wright-Patterson, Dr. Nelson, AFB, Dayton, OH, 1992. Seminar, “Embeded Diagnostics and Built-in Test”, U.S. Army Research Office, Dr. Li-Pi Su, Readstone Arsenal, AL, 1993. Invited talk, “On-line Error Detection in Analog Systems”, Ford Electronics, Dr. G. Moszynski, Detroit, MI, 1993. Panel presentation, “Analog Boundary Scan Cell for Mixed-Signal Testing”, IEEE Working Group P1149.4, Dr. M. Soma, Baltimore, MD, 1993. Invited talk, “Analog Boundary Scan Cell”, Ford Electronics, Dr. S. Stoica, Detroit, MI, 1994. Seminar, “Neural Networks for Image Recognition”, Institute of Electronic Systems, Warsaw Technical University, Warsaw, Poland, August 1994. Invited talk, “Testing of Analog Interconnections”, Ford Electronics, Dr. S. Stoica, Detroit, MI, 1995. Seminar, “Information Based Feature Selection”, Wright Labs, Dayton, OH, 1996. Seminar, “Switch Level MOS Transistor Model for Analog Simulation”, OSU, Columbus, OH, 1996. Invited talk, “Mixed signal testing and design for testability” Ford Electronics, Detroit, MI, Jan. 1997. Seminar, “Iterative wavelet transform in NN learning”, Warsaw University of Technology, Warsaw, Poland, June 1997. Invited talk, “Manufacturing test in IC fabrication of automotive electronics” Delco Electronics, Kokomo, IN, Sept. 1997. Invited lecture, “Feature Selection in self-organized learning for target recognition”, Technical University of Darmstadt, Darmstadt, Germany, Dec. 1998. Seminar, "Signal Clustering in Target Recognition", Wright Labs., Dayton, OH, 1998. Panelist on the Workshop on the Software Embedded System Test, Gaithersburg, MD, Nov. 7-11, 1999. Seminar, "Hybrid Distance and Piecewise Linear Approximation for SAR/HRR Target Identification", Wright Labs., Dayton, OH, 1999. The Keynote Speaker at the System on a chip and Reconfigurable Computing Workshop, Riyadh, Saudi Arabia, 1999. Gave two seminar presentations in Magnolia Broadband, Clinton NJ, on VCO and PLL design for their design engineers. Summer, 2002. Technical design presentation, “Design of 14 bit DAC in 0.13um CMOS”, Terayon Corp. (San Jose California), March, 2002. Seminar, “Collaborative Sensing and Threat Awareness in Urban Operation - Machine Intelligence Approach”, AFRL/SNAT WPAFB, August 2005. Seminar, “Machine Intelligence Approach to Sensing and Vigilance”, AFRL/SNAT WPAFB, August 2006. The Keynote Speaker at the The International Conference on Signals and Electronic Systems, ICSES'06, Lodz, Poland, Sep. 17-20, 2006. Seminar “Challenges of the embodied intelligence”, Institute of Electronic Systems, Warsaw University of Technology, Sept. 2006. The Keynote Speaker at the International Conference on Artificial Intelligence, Siedlce, Poland, Sept. 21-22, 2006. Seminar, “Goal Creation System for Machine Intelligence”, HEIDI group, Ohio University, October 2006. RESEARCH GRANTS AND CONTRACTS FUNDED (TOTAL $3,456,226) Year Sponsor Topic 1984 Valid Logic Inc. Equipment Grant for VLSI lab. $167,010 1986 1987 DARPA/NSF Development of Testing Strategies for Very Large Analog Circuits Software Grant for IBM PC Lab. 22 copies of PC Scheme Fabrication of Prototype VLSI Circuits $ 21,571 1987 National Bureau of Standards Texas Instruments 1987 1989 Stocker Fund 1990 Valid Logic Inc. Development of Testing Strategies for Large Nonlinear Circuits Time Domain and Frequency Domain Testing of Large Nonlinear Circuits Testing Strategies for Large Mixed Mode Circuits Software for Sun Worksations 7 copies of PSpice Deluxe A/D Sun Workstations for VLSI, Microwave and Image processing Lab Software for VLSI design on Sun workstations $ 54,940 1989 National Bureau of Standards National Bureau of Standards National Institute of Standards and Technology Microsim Corporation 1991 Magnetek Corp. Testability Design of PC Power Supplies $ 10,000 1992 A Feasibility Study for On-Line Error Detection in Analog Systems Modeling and Verification Procedures for SelfCalibrating Systems Design and Simulation Software $ 19,965 1994 National Institute of Standards and Technology National Institute of Standards and Technology Mentor Graphics 1996 View Logic WorkWiew Office Software 1997 1997 State Committee for Scientific Research AFOSR $27,535 1997 Sarnoff Research 1 year Grant Supporting Cooperation Between WUT and Ohio University Feature Selection for Automatic Target Recognition Reengineering of Intel 8031 Microprocessor 1998 Xilinx Software and hardware for FPGA $25,922 1998 University of Cincinnati $16,085 1998 1988 National Institute of Standards and Technology Sverdrup Technology Inc. 1998 AFOSR 1999 AFOSR Application of scalability and testability in mechatronic design environment Testing Strategies for Mixed Signal Embedded Systems Evolutionary Feature Extraction for SAR Air to Ground Moving Target Recognition – Statistical Approach Feature Extraction for Air to Ground HRR Radar ATR Based on Mutual Information and Statistical Techniques Feature Selection for Automatic Target Recognition 1988 1989 1994 Amount $ 2,200 $ 6,400 $120,375 $ 50,069 $ 66,950 $46,172 $310,000 $ 23,697 $1,800,000 $30,000 $4,500 $32,197 $44,950 $25,000 $144,180 $27,535 1999 Sarnoff Research Pass Transistor Library Development $9,661 1999 Testing Strategies for Mixed Signal Embedded Systems GPS research $9,636 $75,000 GPS signal acquisition and processing $45,000 2001 National Institute of Standards and Technology Avionics Engineering Center Avionics Engineering Center Xilinx $15,000 2001 Sarnoff Research 10 Spartan Boards, core generator software Design of 14bit DAC in 0.13um CMSO 2002 Magnolia Broadband $26,818 2002 2002 Avionics Engineering Center Xilinx Design of 5.5 GHz CMOS Fully Integrated Tunable VCO GPS signal acquisition and processing 2002 Xilinx 10 Spartan Boards for VHDL lab $8,000 2002 Magnolia Broadband PLL Design for CDMA 2000 in SiGe $14,529 2003 Two Sun-Spark workstations and dedicated FPGA based hardware Design of Integrated VCO for CDMA2000 $50,000 2003 Sensors Directorate, Air Force Research Laboratory Magnolia Brodaband 2003 Xilinx XCV100-5BG560C for SOLAR research 2003 GPS signal acquisition and processing $25,000 2004 Avionics Engineering Center Xilinx System generator and PCI development kit $28,581 2005 AFORS $22,000 2005 EVIS LLC 2006 AFOSR 2006 Anteon Corporation, a General Dynamics Company Collaborative Sensing and Threat Awareness in Urban Operation Equipment grant to design a rowing control system Challenges and Promises of Embodied Intelligence Neural Network Self-Organization and Extracting Video Game Data for Machine Learning Total funds received 2000 2001 480 XCV1000 chips COURSES TAUGHT Graduate: EE616 EE617 EE690 EE690 EE716 EE819 Computer Aided Analysis of Electronic Circuits Design for Testability VLSI Design of Neural Networks Design of Intelligent Systems Active Network Theory Graph Theory $96,000 $30,000 $244,500 $7,250 $3,070 $5,000 $18,000 $16,000 $3,826,298 Undergraduate: EE415 EE414 EE495 EE222 EE312 EE343 EE210 EE411 EE323 VLSI Design VHDL Design ECE Capstone Design Introduction to Digital Circuits Linear Systems and Networks Electronics Circuit Theory Passive Filter Synthesis Analytical Foundations of Electrical Engineering Laboratories: EE401 EE402 VLSI design laboratory VHDL design laboratory THESES AND DISSERTATIONS COMPLETED Master of Science No Name Date Thesis Title 1 Jerzy Romaniuk 1979 Optimization of Railway Traction Using Graph Methods 2 Edward Sliwa 1979 Computer Programs for Analysis of Large Unistor Graphs 3 Zbigniew Calka 1980 4 Jerzy Kotkowski 1981 5 Eric M. Schwarz 1984 6 Hong Dai 1985 Topological Synthesis of Active Networks Using Unistor Graphs Topological Analysis of Switched Capacitor Circuits Using Signal-Flow Graph Representation Parallel Processing and VLSI Design: Solving Large-Scale Linear Systems Network Approach to Impedance Computerized Tomography 7 Venkata S.R. Dandu 1985 8 Fadi M. Kaake 1986 9 1986 10 Venkatram R. Chintala Soheil Davati Parallel Processing and VLSI Design: A High Speed Efficient Multiplier A VLSI-nMOS Hardware Implementation of an IIR Bandpass Orthogonal Digital Filter Digital Image Data Representation 1986 VLSI Implementation of Recursive Digital Notch Filter 11 I-Sheng Yang 1986 An Impedance Scanner (project in non thesis option) 12 George M. Mourad 1986 13 Kang-Chung Chiang 1986 14 Luis A. Montalvo 1986 15 Hoon-Kyeu Lee 1986 16 Samboon 1986 Built-in Testable Structure for VLSI Circuits (project in non thesis option) Scan Path Design of PLA to Improve its testability in VLSI Realization VLSI Implementation of Control Section of Overlapped 3-bit Scanning 64-bit Multiplier Automatic Test Pattern Generation in the Logic Gate Level Circuits and MOS Transistor Circuits A VLSI-nMOS Hardware Implementation of a High Speed Taesopapong Parallel Adder 17 Chung-nan Lyu 1988 Pipelined Floating Point Divider with Built-in Testing Circuits 18 Elie N. Talej 1988 19 Chengbu Kim 1988 20 Chao-Wu Chen 1988 21 Hsein-Jung Mao 1988 A VLSI Design of a Finite Impulse Response Low-Pass Digital Filter One-Dimensional Compaction Strategy for VLSI Symbolic Layout System Design and nMOS Implementation of Parallel Pipelined Multiplier VLSI Design and Implementation of a Parallel Sorter 22 Mohammad Eshghi 1988 Highly Parallel Transversal Adaptive Filters 23 Chin Aik Le 1988 An 8-bit Inner Product Multiplier by Parallel Pipeline Algorithm 24 Chung Chih-Ping 1989 Setting CMOS Environment for VLSI Design 25 Xiaoming Wu 1991 26 Youping Chen 1991 Approximation Using Linear Fitting Neural Network: Polynomial Approach and Gaussian Approach Neural Network Approximation for Linear Fitting Method 27 Sin Wo Kuan 1992 28 Chang-Chyh Hsiao 1992 29 Nasser Ansari 1992 30 Ying-Wei Jan 1994 31 1996 32 Senthilkumar Manickavasagam Zheng Chen 33 Abdulqadi Al_Aqeeli 1998 VLSI Implementation of a High-Speed Delta-Sigma Analog to Digital Converter FPGA Realization of Haar Wavelet for Pattern Recognition 34 1998 A Comparative Study of High Speed Adders 35 Raja D.V. Bhupatiraju Chirag Patel 1999 A Time-to-Voltage Converter 36 Fengjing Qiu 1999 37 Aman Sareen 1999 38 Phillip Southard 2000 Analog VLSI Design of Two-Phase and Multi-Phase Voltage Doublers with Frequency Regulation Reconfigurable Design for Pattern Recognition Using Field Programmable Gate Arrays Design Methodology for Modeling a Microcontroller 39 Sanjeev Gunavardena 2000 40 Zhu Zhen 2002 41 Tsun Ho Liu 2002 42 Guo, Yongtao 2004 1997 VLSI Implementation of Neural Network for Character Recognition Application Design of VLSI CMOS Systems Using MAGIC Handwritten Character Recognition by Using Neural Network Based Methods Segmentation and Clustering in Neural Networks for Image Recognition A+B Arithmetic - Theory and Implementation Feasibility Study for the Implementation of Global Positioning System Block Processing Techniques in Field Programmable Gate Arrays Averaging Correlation for Weak Signal Global Positioning System Signal Processing Future Hardware Realization of Self-Organizing Learning Array and its Software Simulation PicoBlaze Based Self Organizing Learning Array and its Experimental Setting 43 Feng, Wang 2004 44 Li, (Yue) Lily 2006 Energy Efficient Digital Baseband Modulator for Cable Terminal Systems Targeted on Field Programmable Gate Array Active Vision through Invariant Representations and Saccade Movements Philosophy Doctor No Name Date Dissertation Title 1 Hong Dai 1989 2 1990 3 Mohamed Abd ElGamal Chiung-Hsing Chen Development of Decomposition Approach for Testing Large Analog Circuits Fault Location and Parameter Identification in Analog Circuits 4 Xuefeng Fang 1994 5 Sinkuo Chai 1995 6 Zhi-Hong Liu 1998 7 Ying-Wei Jan 1998 8 Dale Nelson 2001 9 Ahmad Alsolaim 2002 10 Abdulqadir Alaqeeli 2002 11 Pang, Jing 2003 12 Liu, Dong 2003 Inner-Product Based Signal Processing: Algorithms and VLSI Implementation Small Area, Low Power, Mixed-Mode Circuits for Hybrid Neural Network Applications Multiclassifier Neural Networks for Handwritten Character Recognition Mixed-Signal Testing of Integrated Analog Circuits and Modules A Switched-Capacitor Analysis of MOS Circuit Simulator: SAMOC High Range Resolution Radar Target Classification: A Rough Set Approach Dynamically Reconfigurable Architecture for Third Generation Mobile Systems Global Positioning System Signal Acquisition and Tracking Using Field Programmable Gate Arrays Direct Global Positioning System P-Code Acquisition Field Programmable Gate Array Prototyping Analog and Mixed Signal Test and Fault Diagnosis. 13 Ding, Mingwei 2005 High Level Design Methodology for Reconfigurable Systems 14 He, Haibo 2006 15 Zhen, Zhu 2006 Dynamically Self-Reconfiguarable Systems for Machine Intelligence Characterization of Global Positioning System Earth Surface Multipath and Cross Correlation for Aircraft Precision Approach Operations using Software Radio Technology 1994 PROFESSIONAL ACTIVITIES Professional memberships Senior Member of the Institute of Electrical and Electronics Engineers - Circuits and Systems Society - Computer Society Member of the American Society of Naval Engineers Member of the Association for Computing Machinery Member of American Society for Engineering Education Member of the Association of Professional Engineers of Ontario Referee of journals IEEE Transactions on Circuits and Systems, IEEE Transactions on Computers, IEEE Transactions on Neural Networks, IEEE Transactions on Instrumentation and Measurement, IEEE Transactions on Computer Aided Design, IEEE Transactions on Design and Test of Computers, IEEE Transactions on Electromagnetic Compatibility, IEE Proceedings-G Circuits, Devices and Systems, International Journal of Circuit Theory and Applications, International Journal Computers and Mathematics with Applications, Journal of Electronic Testing, Journal of Neurocomputing, Kluwer Academic Publishers, Elsevier Engineering Applications of Artificial Intelligence, Bulletin of International Rough Set Society, Archiwum Elektrotechniki. Referee of conferences International Conference on Artificial Intelligence and Applications, International Conference Artificial Neural Networks, International Conference on Signals and Electronic Systems, International Multiconference on Computer Science and Information Technology, ACM/IEEE Design Automation Conference, Artificial Neural Networks in Engineering, Design Automation and Test in Europe, European Conference on Circuit Theory and Design, IEEE International Conference on Computer Design: VLSI in Computers, IEEE International Symposium on Circuits and Systems, IEEE VLSI Test Symposium, International Conference on VLSI Design, International Conference on Parallel Processing, International Test Conference, International Workshop on Intelligent Signal Processing and Communication Systems, Midwest Symposium on Circuits and Systems, OAI Workshop on Neural Networks. COMMITTEES AND SERVICES Professional Service International Program Committee Member, IASTED International Conference on Artificial Intelligence and Applications, Innsbruck, Austria, Feb. 12-14, 2007. Scientific Committee Member, The International Conference on Signals and Electronic Systems, ICSES'06, Lodz, Poland, Sep. 17-20, 2006. Technical Committee Member, First International Multiconference on Computer Science and Information Technology, Wisla, Poland, November 6-10, 2006. Session Chair, International Conference Artificial Neural Networks, Warsaw, Poland, Sep. 11-15, 2005. Founding Member of the Institute for Applications of the Mathematical Sciences at Ohio University, 2004. Technical Committee Member, International Conference Design Automation and Test in Europe, Paris, France, Feb. 16-20, 2004. Technical Committee Member, International Conference Design Automation and Test in Europe, Paris, France, March 2002. Member of NSF Information Technology Research (ITR) panel, 2001. Board of Examiners, Indian Institute of Technology, Delhi, India, 1999. Technical Committee Member, Workshop on the Software Embedded System Test, Gaithersburg, MD, Nov. 7-11, 1999. Planning Committee Member, Edison Electronic Technology Center in Ohio, 1998. IEEE Working Group for P1149.4 Mixed-Signal Test Bus Standards 1992-1997. Technical Program Committee Member, OAI Neural Networks Symposium 1995. Technical Program Chairman, IEEE Southeastern Symposium on System Theory 1994. Technical Program Committee Member, International Workshop on Intelligent Signal Proc. and Communication Systems 1993. Technical Committee Member, European Conference on Circuit Theory and Design, Warsaw, Poland 1980. University and College Committees Institute of Electronic Fundamentals, Director's Advisory Committee (1978-80). Stocker Fund Planning and Advisory Committee (1991-95, 2005-). Ohio University Library Committee (1996-98) Graduate Council (1985-88). Chairman of the Fellowship Board (1998). Policies and Regulations (1999). Graduate Research Council (2004-2006). Departmental Committees Chairman of VLSI Committee (1983- ). Chairman of Research Committee (1991-99). Chairman of ECE Library Committee (1991-97). Graduate Committee Chairman in Networks and Electronics (1983- ). Computer Committee (1983/84). Curriculum Committee (1986/87). Core Courses Committee in Circuits and Analytics (1994-1996). Chairman of the ECE Seminar Series (1985-87, 1996-97). Www Committee (1998-2002). Annual Review and Raise Allocation Advisory (2000-2003). Undergraduate Course Committees: EE Senior Design Committee, Advanced EE 3**,4** (2000-) Promotion and Tenure Committee (1994-1997, 2003-2006) HONORS AND AWARDS Listed in Who's Who in Engineering Education Award of the Ministry of Science and Higher Education for outstanding research Outstanding teacher award Technical University of Warsaw Honor Society - Eta Kappa Nu Nominated to the Outstanding Graduate Faculty Award at Ohio University twice. The Keynote Speaker at the VII Riunione Annuale Dei Ricercatori, Trani, Italy. The Keynote Speaker at the System on a chip and Reconfigurable Computing Workshop, Riyadh, Saudi Arabia, 2000. Best paper award in Mathematical Methods and Optimization in Problem Solving System - 4th World Multiconference on Systemic, Cybernetics and Informatics, Orlando FL, July, 2000. Certificate for outstanding inventive contributions to Ohio University Intellectual Property 1999-2000. Best paper award at the SPIE 15th Annual Int. Symp. on Aerospace/Defense Sensing Simulation and Controls, Orlando FL, April 2001. The Keynote Speaker at the The International Conference on Signals and Electronic Systems, ICSES'06, Lodz, Poland, Sep. 17-20, 2006. The Keynote Speaker at the International Conference on Artificial Intelligence, Siedlce, Poland, Sept. 21-22, 2006.