it04041.doc
Description: Researchers at Intel are working on ways to cost-effectively and rapidly move large amounts
of data within computer systems, and have designed new optical interconnect technology that can address
the bandwidth limitations of metal interconnects in future-generation computing systems.
Keywords: Optical I/O, VCSEL arrays, photodetector arrays, polymer waveguides, hybrid packaging, flipchip.
Initiatives and Technologies
Intel Introduces Chip-to-Chip Optical I/O Interconnect
Prototype
Ian Young
Intel Fellow, Technology and Manufacturing Group
Director, Advanced Circuit and Technology Integration
Intel Corp.
Overview: Unwiring Chips
Optical interconnect technology, in the form of fiber optics, has been used for decades in longdistance applications, such as telephony and wide area networks, and in recent years has made
inroads into shorter-distance applications, such as communications between servers in a data
center. Now, optical interconnect is showing promise for ultra-short-reach applications in its ability
to support far higher bandwidth than the metal wires that now carry data from board to board,
chip to chip, and component to component within a single chip.
While still some years from viability in a production environment, the technology has been
demonstrated by a team from the Intel Components Research Lab in a fully functioning prototype
device that attained an aggregate bandwidth of more than 8 Giga-Transfers per second. This
article describes the state of the technology in general, the architecture and basic design of the
Intel prototype device, and the implications of its development.
Addressing Bandwidth Limitations
With the continued growth in the integration density of CMOS (complementary metal-oxide
semiconductor) and clock frequency of microprocessors, the aggregate bandwidth required
between future-generation microprocessors and chipsets or between multiprocessors on a
motherboard will increase sharply. For example, in about 5 years CMOS-based transistors will
be fast enough for transceivers to operate at clock speeds of roughly 14 GHz, fast enough to
support data-transfer rates of 20 Gbps. This will seriously challenge the current copper-tracebased technology, which is considered likely to top out at 15-20 Gbps due to the significant signal
degradation, power dissipation, and electromagnetic interference that are unavoidable at higher
clock speeds.
Manufacturers have sought to address the limitations of copper by increasing the thickness of the
traces, using more exotic substrate materials with lower dielectric loss tangents, and employing
differential signaling techniques or more sophisticated I/O drivers at the transmitter and receiver.
However, all these potential solutions are costly, thereby making optical interconnect technology
an increasingly attractive alternative.
Optical interconnect technology could begin to play a significant role by the middle of this decade.
Around 2006 or 2007, we expect to see commercial-level optical interconnect technology at the
board-to-board level, and sometime in the 2010s at the chip-to-chip level.
Optical interconnect technology has been used for decades in long-distance applications such as
telephony and the Internet, and in recent years it has been applied to shorter-distance
applications such as computer-to-computer, rack-to-rack, and network-to-network
communications. Such applications have proven that even at high frequencies, optical fibers and
waveguides can support an unlimited distance-bandwidth product as compared with electrical
cables, with minimal loss in signal and almost no cross-talk.
Still, optical interconnect technology in the ultra-short-reach setting poses its own cost problems.
The technology depends largely on components made of gallium arsenide and germanium, which
are more expensive than silicon. Alignment is also a more delicate matter in optical technology,
and for this reason optical equipment has been difficult to design and build. Consequently, current
research is focused on ways to make the technology more cost-effective, particularly from a
manufacturing standpoint. Ultimately, an optical solution could replace electrical interconnect
when it has higher performance at lower cost and strong manufacturability in high volume.
Intel’s Optical Solutions
Toward that end, researchers at the Intel’s Components Research Lab are matching highperformance optical components, such as vertical-cavity surface-emitting lasers (VCSELs), with a
cost-effective and industry-compatible packaging solution based on low-power CMOS
transceivers and standard high-volume microprocessor packaging technology. Most recently this
research culminated with the January 2004 demonstration of a fully functioning prototype device
that reached aggregate speeds of more than 8 Giga-Transfers per second.
The device is a high-speed 12-channel link (8 data channels) with a parallel CMOS optical
transceiver packages. The optical I/O is based on an optoelectronic flip-chip pin grid array
(FCPGA) package, and the key components of the hybrid package are gallium arsenide VCSELs,
p-type intrinsic n-type doped silicon (PIN) photodiode arrays, acrylate polymer waveguide arrays,
multiterminal fiber-optic connectors, and the CMOS transceiver chip.
These components are flip-chip mounted on top of the FCPGA organic substrate to enable
parallel point-to-point optical transmission. During complete-link optical transmission, VCSEL
arrays are directly modulated by CMOS drivers with non-return to zero (NRZ) data signals with
source-synchronous clocking and coupled to multimode polymer waveguide arrays for
transmission to a receiver array that consists of gallium arsenide photodiodes and on-chip
transimpedance amplifiers. Test circuits residing on the CMOS chip enable bit-error testing of the
optical transmission link.
Architecture and Design
The optoelectronic transceiver chip is an integral part of the chip-to-chip optical I/O development
effort. Designed and fabricated in 0.18-micron digital CMOS process technology, the 3 x 3.25 mm
transceiver chip occupies only one-third of the total chip area while containing all the circuits
needed for use in optical-link transmission.
The key units of the chip are 12 VCSEL drivers and 12 receivers that consist of transimpedance
and limiting amplifiers, a clock unit, a tester unit, and a scan chain for testing. Of the device’s 12
channels, two provide DC signals for alignment of optoelectronic chips with waveguide arrays,
two generate clock signals, and the remaining eight transmit PRBS NRZ (pseudo random bit
sequence non-return-to-zero) data signals to drive the VCSEL arrays. The PRBS data is
generated by the clock from a voltage-controlled oscillator that drives a 15-bit linear-feedback
shift register (Figure 1).
CMOS Chip
Data
Clock
Figure 1. Physical placements of optical and electrical components on FCPGA package.
The receiver-array circuitry consists of transimpedance amplifiers (TIAs) and limiting amplifiers
(LIAs). Each TIA, which has a 2.5-kiloohm feedback resistor, was designed assuming a 500femto-Farad total capacitance that comes from the solder bumps, ESD, and parasitic capacitance
of the photodetector. The TIA/LIA system is single-ended with the noninverting terminal providing
a DC reference input signal to adjust the DC bias of the photodetector. Input current signals from
the photodiodes to the TIA pass through three stages: differential, amplification, and inversion.
The LIA generates digital levels from analog signals, and the output driver drives the digital signal
off-chip.
As for the package, researchers were careful to design an architecture that would be compatible
with current microprocessor package technology while supporting the integration of low-cost,
high-performance optical components. Their work resulted in a six-layer organic substrate
measuring 35 x 35 mm with a standard build-up thickness consisting of laminated copper layers
separated by dielectric.
The physical layout of the package includes VCSEL and photodiode array chips, multiterminal
connectorized polymer waveguide arrays, decoupling capacitors, and miniature RF connectors,
all attached to a common organic substrate. Because total thickness of the waveguide exceeds
100 microns—25 microns greater than the maximum height of solder balls—the substrate
includes a trench to provide the necessary clearance from the optoelectronic chips. The physical
layout also includes multiterminal fiber-optic connectors on either side of the package to simplify
system and component-level testing.
The electrical design of the package involves the routing of signal and power lines as well as the
use of decoupling capacitors. All the electrical lines on the substrate are routed as controlled
impedance (50-ohm), 2.5-GHz microstrip lines. The copper traces used to interface with
optoelectronic chips are routed on the top surface of the FCPGA package to maintain signal
integrity. The microstrip lines originating from the driver and receiver section of the CMOS chip
are equalized to avoid any skew between clock and data for the source synchronous architecture.
To minimize frequency-dependent loss on the microstrip traces, the CMOS transceiver chip is in
close proximity to the optoelectronic array chips. Each of the six layers of the substrate is
assigned for distribution of signal, power, and biasing. High-speed clock (Xc) and data (Xd)
signals are measured directly from the substrate using miniature radio frequency (RF)
connectors. Decoupling capacitors are used on the top and landside of the package to provide a
return path from the lasers to the driver chip and to minimize power-supply noise. Bias planes are
used to externally bias VCSELs and photodiodes.
To permit simultaneous optical communication among more than two chips, the optical assembly
on the substrate has transmitter and receiver portions that are symmetrically situated with respect
to the CMOS transceiver chip at the center of the substrate. Within this assembly are gallium
arsenidebased, oxide-confined, top-emitting VCSELs and gallium arsenide PIN photodiode
arrays with coplanar contacts. The transmitter includes a VCSEL optical-source array and a
polymer waveguide array, coupled with 45o metal mirrors to direct light at a right angle for
transmission through the waveguide.
Similarly, the receiver consists of an identical optical waveguide assembly to the transmitter
section with a high-speed gallium arsenide photodiode array replacing the VCSEL array. In this
device, the interfacing of optoelectronics chips and waveguides is unique in that optoelectronic
chips are flip-chip bonded with their apertures face down on the substrate to enable polymer
waveguides to slide under and couple to the surface of optoelectronic chips. This arrangement
enables separate testing of the polymer waveguides after attachment to the substrate, thereby
helping to isolate the influence of the packaging environment. (See Figure 2.)
Figure 2. A completed prototype package for chip-to-chip optical data communication. The MT (multiterminal) connector is magnified to show the light output from the 12 channels of the transmitter.
The optical coupling efficiencies at the ends of the package waveguides constitute a critical
performance parameter in the interconnect architecture. Using experiments and simulations, the
research team determined the optical misalignment tolerance of the system to be in excess of
±10 microns, both transverse to the waveguide and along its axis, for 1dB half-width (roughly 80
percent efficiency from maximum coupling). This tolerance range allowed passive alignment of
the VCSEL and photodiode dies to the waveguide arrays.
Another key parameter of the interconnect architecture is the optical-loss budget, including the
total VCSEL/photodiode-coupling loss to the 45o mirror on either side of the optical link,
propagation loss through the waveguide, multiterminal connectorization loss, and Fresnel losses
at the interfaces of connectors. Based on various parameters of individual optical components,
the total optical loss budget for the complete link was calculated to be between 7dB (best case)
and 12dB (worst case).
Summary
Optical interconnect technology appears to be a promising candidate for successfully addressing
the bandwidth limitations of metal interconnects in future-generation computing systems. To
realize the potential of optical interconnect technology for ultrashort distances, researchers are
focusing on an architectural and manufacturing approach that will be cost-effective and practical.
Researchers at Intel’s Components Research Lab have taken a significant step in that direction
by developing a prototype device that is based on low-power CMOS transceivers and highvolume commodity packaging technology. By building many of the device components on a
standard CMOS process, the researchers have sought to remove some of the inherent difficulties
of optical interconnect technology and provided a foundation for chip-to-chip interconnects over
the next decade.
More Info
Visit the Intel Web site for more information on Intel’s silicon technologies.
[http://www.intel.com/research/silicon/]
To learn more about some of the work Intel is doing in optoelectronics, visit the Intel Silicon
Photonics Web site. [http://www.intel.com/labs/sp/]
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Author Bio
Intel Fellow Ian Alexander Young is the Director of Advanced Circuit and Technology Integration
within the Technology and Manufacturing Group. He is responsible for defining and developing
future circuit directions and optimizing the manufacturing process technology for highperformance microprocessor products. He is also responsible for the development of clock
generators for microprocessors, and identification of new CAD design tool requirements and
circuit modeling capabilities for high-performance and low-power design.
Young, a native of Melbourne, Australia, received his bachelor's and master's degrees in
electrical engineering from the University of Melbourne, Australia. He received his Ph.D. in
electrical engineering from the University of California, Berkeley. Prior to joining Intel, Young
worked on analog/digital integrated circuits for Telecommunications at Mostek Corporation, and
did consulting work.
Young has written many articles for technical publications, and has received two Intel
Achievement Awards. He has been the inventor or co-inventor of numerous patents and patents
pending, and has been a member of the Intel Patent Review Committee (TMG) since 1993, as
well as other Intel groups. He is a member of many professional organizations, including IEEE,
and has been a senior member of IEEE since 1996.