Simulations of the initial circuit
Following the calculations of the circuit, it was implemented as a schematic and simulated. The following discusses the process of simulation and shows some of the results obtained. Most of the simulation states used were based off of the given simulation states.
To simulate the circuit, the schematic shown in Figure 1 was used. A minor modification was made to
the original by the addition of a grounding resistor connecting the in_neg net to vss. This was used to assist in the simulation, since some strange behavior was observed when the resistor was left out.
When the node was intended to be disconnected from vss, it was set to a large value, while it was set to a small value when it was intended to be shorted to vss.
Figure 1 Schematic used to test the op-amp
Unity Gain Bandwidth (UGBW)

The first set of simulations measured the low frequency gain, the input capacitance, the unity gain
bandwidth and the phase margin. The plot obtained from this simulation can be seen in Figure 2. As
can be seen, the phase margin is quite large, but this occurs because the phase rises slightly before the unity gain frequency. It can be seen, though, that the phase is always at least 90 degrees away from 180 degrees below the unity gain point, so the op-amp should be very stable and should have no overshoot.
Figure 2 Plot from the UGBW simulation
Output resistance
In order to measure output resistance, the appropriate state was loaded, which changed the voltage to which the output resistor was connected to. By measuring the difference in output current, the resistance could be calculated.
Noise simulation
To determine the noise of the circuit, the noise simulation state was loaded and run. A plot of the
equivalent input noise from 1 kHz to 1 MHz can be seen in Figure 3. As can be seen, both 1/f noise and
white thermal noise played a significant role.
PSRR simulations
To determine the power supply rejection ratio, the appropriate state was loaded. The supply voltages were varied and the change in the output was observed. The gain between the two was compared to
the circuit’s differential gain. The appropriate graphs can be seen in Figure 4 and Figure 5.
CMRR simulation

To determine the common mode range, the appropriate state was loaded. The simulation was similar to the PSRR simulation, only with the voltage common to the differential inputs varied instead of varying the power supply. The graph generated can be seen in
CMR simulation
In order to determine the common mode range, the common mode input was swept while observing the output. The common mode range is thus determined by observing the entire possible range of common mode voltage over which the output is not saturated. The plot obtained from the appropriate simulation sate can be seen in Ошибка! Источник ссылки не найден., from which the common mode range can be seen to be 1.355 V.
Figure 3 Plot of equivalent input noise of circuit

Figure 4 Plot from PSRR+ simulation
Figure 5 Plot from PSRR- simulation

Figure 6 Plot from CMRR simulation
Figure 7 Results of CMR simulation
Voltage offset and power simulation
To measure the input offset voltage, a simulation was run with the DC operating being saved. The voltage offset was calculated as the difference between the positive and negative voltages when ideally both should be 0.
Maximum current simulation

To measure the maximum current, the output was both shorted to vss and then to vdd, with the resultant output current being measured.
Rise/Fall test
To determine the rising, falling, and settling time, the op-amp was configured in unity gain configuration in a new schematic. The circuit was fed a pulse train with very fast rising edges, and the response of the
output was observed. One such output can be seen in Figure 8. From this graph, the rising time (taken
by the difference between the 10% and 90% points) and falling time (taken by the difference between the 90% and 10% points) as well as the settling time (taken as the time it takes to reach 99% of its final value) was measured. As can be seen from the plot, the rising response is not as good as the falling response. Although it quickly reaches most of the final value quickly, the last section is somewhat slower. Thus, the rising time is fairly good, but the rising settling time is not as good. In all cases, the parameters meet the required specifications. Since the phase margin is quite large, no overshot or
undershoot was observed. This can be seen in Figure 9 and Figure 10.
Figure 8 Results of transient simulation

Figure 9 Close-up of transient simulation results showing no undershoot
Figure 10 Close-up of transient simulation results showing no overshoot

THD
In order to find the total harmonic distortion, a transient simulation with a 10 kHz input sine wave was run with the op-amp in unity gain configuration. The THD of both the input and output was observed, with the added distortion being the output value minus the input value. A discrete Fourier transform
was calculated using the output values. An example of one can be seen in Figure 11.
Figure 11 Plot from the THD simulation