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HYTEC VME – DOT-RX 2338
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12 CHANNEL LVDS/OPTICAL
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DATA RECEIVER MODULE
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TECHNICAL MANUAL
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AND CIRCUIT DESCRIPTION
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HYTEC ELECTRONICS LTD.,
64 AMY STREET
LEICESTER
ENGLAND
LE3 2FB.
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CONTENTS
1.
Introduction
2.
DAT-RX Module - Register Set Overview
3.
Setting Up - Jumpers
4.
VME Interface - Full Register Set Description
5.
Control and Status Register Format
6.
Interrupts
7.
Detailed Operating Sequence
8.
Pin Connections
9.
Indicators
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Introduction
This single width 6U high VME module contains 11 differential ECL data outputs, one differential ECL
clock output, a mark/space balancer circuit and an LVDS differential input stage. There are twelve LVDS input
pairs carrying eleven data lines, and one clock. A parallel optical input stage is provided as an option for the
same twelve signals. The unit uses J1 and J2 as standard for the normal VME interface and JAUX for ECL power
rails and optional geographical addressing.
2.
DAT-RX Module - Register Set Overview
The module is equipped with a complete set of VME registers in A16 (short addressing) space, in line
with Hytec's standard scheme which is modelled on the VXI Configuration Register set.
This register set comprises the following:a)
b)
c)
d)
e)
f)
g)
An ID register, indicating manufacturer and type.
A vector register, for programming interrupt acknowledge data.
A Model Code register, showing 2338 decimal, the unit's type no.
A Control and Status Register through which the unit is
controlled and its status observed.
A Memory Attributes Register, not used.
A Memory Offset register, not used.
An RX DATA Register for test purposes.
3.
Setting Up - Switches and Jumpers
Before installing the module, there are some jumpers to configure as follows:Jumper J7 selects the address selection mode. This can be either jumper selection or geographical address. If
the unit is used in a CERN specification V430 crate with JUAX (the centre 30-way DIN connector) with
geographical addressing, remove J7 and the module’s start address in A16 space will be set automatically
Jumpers J6 to J2: These set the board's VME Base address in A16 (short addressing) space when jumper J7 is
IN – jumper selection mode.
Jumpers J6 to J2 ‘OUT’ or ‘IN’ select '1' or '0' respectively for each of 5 address lines. J6 corresponds to address
line A13, J2 to A09. The jumper ‘OUT’ means that the corresponding address line must be a '1', jumper ‘IN’
means the address line must be '0'. Address lines A15 and A14 must both be '1' to start at HEX C000 in line with
Hytec's standard 'VXI' scheme.
For example: To select D600 as the start address:
A15
1
A14
1
fixed fixed
A13
0
A12
1
A11
0
A10
1
A09
1
J6
J5
J4
J3
J2
IN
OUT
IN
OUT OUT
A08
x
A07
x
A06
x
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VME Interface - Full Register Set Description
All registers in this module should be accessed in 16-bit mode, that is they are all D16 compatible. For some, the
'top half' has no meaning, but accesses to these will have no effect.
Running through our 'Overview' list (sect. 2), the following is a full description of the format and function of each
register (see Fig. 1).
Item
Name
Offset from Base Address (HEX)
a)/b)
ID/Vector
+ 00h
The ID register and Vector register are at the same address. You read the ID and write the vector. The Vector
can be read back for diagnostic purposes at offset 0Ch.
Reading the ID gives HEX FF7F, where 'F7F' on bits 0-11 is Hytec's unique VXI identifier, and 'F' on bits 12-15
means that this unit is A16 register based unit only.
Writing an 8 or 16-bit number to this location (D0-D7 or D15) stores a vector with which it will respond during
interrupt acknowledge cycles.
c)
Model Code
+ 02h
This simply shows the unit's Hytec catalogue number, which is 2338 decimal.
d)
Control and Status Register + 04h
This is a 16-bit register (CSR for short) through which the DAT-RX module is controlled and its status observed.
It implements first a RESET system, which is used to provide a software reset function. In addition to this, there
are several 'fixed' bits, which derive from the VXI spec. and then the following:i) Interrupt Enable - one bit to enable the output of the logic as an interrupt source.
ii) Three bits, IPL0, IPL1 and IPL2 which correspond to the IRQ line to be driven and which level of interrupt
acknowledge to respond to (see section 6).
iii) An Output Enable bit for controlling the output of the incoming data buffer.
iv) An RX Enable bit for the fibre-optic laser receiver.
iv) An RX DETECT bit (read only) showing the presence of an incoming clock.
iv) An SD01 bit (read only) from the fibre-optic laser receiver.
iv) An SD12 bit (read only) from the fibre-optic laser receiver.
Other bits are described in more detail in section 5.
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VME Interface - Full Register Set Description (cont.)
e)
Offset register
+ 06h
Not used.
f)
Memory Attributes Register + 08h
Not used.
g)
RX DATA/TEST Register + 14h
In NORMAL mode, that is with the OEL bit in the CSR set to zero, this register shows the current state of the
received data on bits 0-10. If the OEL bit is written to ‘1’, the incoming data is ignored and data written to this
register at offset 14h is used to drive the ECL outputs. In this mode, reading this register gives you the last data
written.
The front panel LED’s reflect this data also, that is either the incoming data or the test pattern.
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Control and Status Register Format
The format of this register is as follows:15
x
RST:
14
x
13
x
12
x
11
10
09
08
07
RXDET ENRX SD01 SD12 INTEN
06
x
05
04
03
02
OEL IPL2 IPL1 IPL0
01 00
1 RST
Writing a ‘1’ to this bit resets the control logic.
IPL2, 1,0: These select the IRQ line to be driven and the level that the card will respond to with its interrupt
acknowledge vector.
OEL: This (when set to ‘0’) enables the outputs of the data buffers. Writing a ‘1’ to this bit disables these
signals.
INTEN: This bit enabled the IRQ output of the board. ‘1’ = enabled.
SD01: (read only) A status bit from the fibre-optic receiver to show it is receiving valid data.
SD12: (read only) A status bit from the fibre-optic receiver to show it is receiving valid data.
ENRX: This bit controls the ENRX or ‘enable receive’ input to the optical receiver.
RXDET: RX DETECT. Set to ‘1’ by receipt of a stream of clock pulses from the LVDS receivers.
Other bits:
‘1’ means always read as ‘1’, writing has no effect. ’x’ means reserved, can be written and read.
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Interrupts
The interrupt output of the unit is the logical OR of the interrupt source bits ANDed with the INTEN (interrupt
enable) bit.
At the time of writing, there are no interrupt sources in this unit. Sources will be added later as required.
7.
Detailed Operating Sequence
When powered on, this unit will be in a defined ‘default’ state in which it requires no intervention from VME in
order to receive and time the incoming data. Only if you wish to impose your own test conditions do you need to
give this module any commands over the VME bus.
8.
Pin Connections
The LVDS inputs connect to a 26-way header. Pins 1-22 carry the eleven data inputs RX0+/- to RX10+/-, with the
positive inputs again on the odd numbered pins. Pins 23 and 24 carry the receive clock.
The data signals each go to a piece of logic, which attempts to recover their timing using exclusive OR gates to
produce their original state in combination with the received clock. The data signals then go to the input logic and
ECL drivers and then to the front panel connectors.
There is one 34-way header on the unit. This carries differential ECL output channels 0-10, with the positive
output signals on the odd pin numbers.
This header also carries the received clock in differential ECL form, again with the positive ECL output on the odd
pin number.
9.
Indicators
The unit carries twelve front panel indicator LEDs. The lowest one, nearest to the 34-way input connector, flashes
every time the unit detects its VME address. The eleven LED’s above this show the state of the input data, either
from the LVDS/Optical link inputs or from the internal test register. An LED ‘ON’ in this section indicates that the
signal is at a logical ‘1’. The top-most LED indicates the state of the least significant bit.