T1E1.2/2000-041
Working Group T1E1.2
Lisle, Illinois May 1-5, 2000
TITLE: Discussion of Robbed-Bit Signaling and Robbed-bit
Writeover (Bit Robbing in Tandem Digital Switches)
SOURCE: Maynard Wright
TTC
9855 Scranton Road
San Diego, CA 92121
Phone: 916-726-1673
858-623-2573
Fax: 858-623-2208 wrightm@ttc.com
_____________________________
This contribution discusses robbed-bit signaling and the associated robbed-bit writeover that occurs when a DS0 is passed through a digital message switch or through a DCS 1/0 cross-connect system.
The information here is intended for use by T1E1.2 in discussing several matters involving robbed-bit signaling and robbed-bit writeover.
This contribution has been prepared to assist Standard Committee T1 -
Telecommunications. This document is offered to the Committee as a basis for discussion and is not a binding proposal on TTC or any other company. The requirements are subject to change in form and numerical value after more study. TTC specifically reserves the right to add to, amend or withdraw the statements contained herein.
* CONTACT: Maynard Wright; email: mwright@ada.com; Tel: 916-726-1673; Fax: 619-623-2208

T1E1.2/99-041
1. INTRODUCTION
Robbed-bit signaling is described in Clause 4 of T1.403.02 [1]. Robbedbit writeover is described by Messerschmitt in [2], but will be described in more detail here. The intent of this contribution is to provide information for use in discussing the V.90 modem problems that were presented to T1E1.2 in February, 2000 by Jack Douglass of Conexant, chairman of TR30.3 as well as for use in discussing the digital tandem channel unit proposed by Lucent [5].
When the information carried by a DS0 channel [3] is extracted from a
DS1 signal incoming to a digital switch and is written into a DS0 time slot in a different outgoing DS1 signal, the frame and superframe structures of the two DS1s will, in general, not be synchronous with each other even if both DS1s are timed such that their bit rates are synchronous or plesiochronous [4] with each other.
The incoming DS0 information must therefore be delayed in the digital switch buffer until it may be written into the proper DS0 time slot in the outgoing DS1. Since the DS0 may carry signaling data in the sixth and twelfth frames if the DS1 is superframe (SF) formatted or in the sixth, twelfth, eighteenth and twenty-fourth frames if the DS1 uses the extended superframe (ESF) format, complete alignment with the outgoing
DS1 will require up to 1.5 ms of one way delay (3.0 ms round-trip) for
SF or 3.0 ms (6.0 ms round-trip) for ESF.
In order to avoid causing the DS0 to undergo delays of this magnitude, a technique called “robbed-bit writeover” or “bit robbing” is generally used. The information extracted from the incoming DS0 is delayed only enough to ensure that it is written into the correct DS0 time slot in the next outgoing frame, without regard to superframe alignment between the incoming and outgoing DS0s. This requires a maximum one way delay of 125  s (250  s round-trip: see Note 1).
Note that, unless the signaling bits are aligned by chance, the bits carrying the robbed-bit signaling data will not be located within the signaling frames of the outgoing DS1. In order to pass the signaling data correctly, the switch determines the state of each incoming signaling bit in the received DS0 and writes that state into the eighth bit of each outgoing DS0 byte that occupies a signaling frame.
This technique writes over transmission information with signaling data and causes bits that were formerly carrying signaling data to be misinterpreted by the distant DS0 demultiplexer as information bits. This corruption of the digitally encoded analog signal can degrade the signal-to-noise ratio by between 1 and 2 dB in the initial tandem switch
[2]. Subsequent passes through additional switches may degrade the signal even more until the total drop in signal-to-noise ratio approaches 6 dB.
An alternate approach is suggested by Messerschmitt’s [2] second note on page 1025. The DS0 might be delayed by a maximum of six frames so that incoming signaling frames would be written only into outgoing signaling frames. The possible misalignment of the A and B (SF) or A, B, C and D signaling bits would be handled by passing the signaling information around the switching matrix as is done when using robbed-bit writeover.
The maximum round-trip delay resulting from such a scheme would be 1.5 ms for both SF and ESF formats.
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2. EFFECTS OF DELAY
If exact superframe alignment of the incoming and outgoing DS0s is achieved by delay, the maximum round-trip delay required is 6 ms for ESF or 3 ms for SF. As pointed out in Section 1 of this contribution, the round-trip delay might be reduced to a maximum of 1.5 ms by using only partial superframe alignment with a maximum of six frames of delay in each direction and by then passing the signaling states around the switching matrix as is done when robbed-bit signaling is used.
The maximum round-trip delay within the local exchange network specified by Section 8 of GR-499-CORE [6] is 0.32 ms for the equipment involved in a transport system with no intermediate terminals. An additional delay is allowed based on the route mileage.
Clause 4.7.2 of ANSI T1.506 [7] allow up to 10 ms of round-trip processing delay between the NI and the POT, again providing an additional allocation for the length of the circuit (Note 2). The allocation for the terminal equipment is based, however, on a more complex circuit than is specified in [6], and the amount of round-trip delay that is allocated to a DCS, the network element that most closely approximates the functionality proposed in [5], is 1.5 ms. The use of the partial superframe alignment technique would thus consume the entire allocation of delay allowed by [7] without leaving any margin for DS1 slip buffers or other delays in the terminal equipment.
3. PROBABILITY OF WRITEOVER
Since 1 in 6 DS1 frames carry signaling data, the probability that robbed-bit writeover will degrade a DS0 during its first pass through a digital switch is 5 in 6. The probability that subsequent passes through additional switches will eventually write over all the encoded analog information that is carried in bit 8 of each DS0 is finite but low.
Messerschmitt notes [2] that a closed form expression for the probability that a particular number of additional signaling bits will have been overwritten after the DS0 has been passed through a specified number of switches is not available. [2] does, however, give an iterative procedure for determining the required probabilities and the values in Table
1 were obtained by using that procedure.
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1 2 3 4 5 6
-----------------------------------------------------------------
1 1 0 0 0 0 0
2 0.16667 0.83333 0 0 0 0
3 0.02778 0.41667 0.55556 0 0 0
4 4.62963e-3 0.16204 0.55556 0.27778 0 0
5 7.71605e-4 0.05787 0.38580 0.46296 0.09259 0
6 1.28601e-4 0.01993 0.23148 0.50154 0.23148 0.01543
7 2.14335e-5 6.75154e-3 0.12903 0.45010 0.36008 0.05401
8 3.57225e-6 2.26838e-3 0.06902 0.36458 0.45010 0.11403
9 5.95374e-7 7.59102e-4 0.03602 0.27756 0.49661 0.18904
10 9.92290e-8 2.53530e-4 0.01852 0.20305 0.50637 0.27181
Table 1
In Table 1 the horizontal legend represents the number of information bits per six frames that have been overwritten and the vertical legend represents the number of switches through which the DS0 has been passed.
Using Messerschmitt’s convention [2], the first “pass through a switch” represents the initial robbed-bit writeover performed at the transmitting DS1 terminal. The overwriting of exactly one bit per six frames is thus certain (probability = 1) for that value.
An alternate presentation of the data, suggested by Steven Bench of TTC, plots the probability that, after a particular number of switches have been traversed by the DS0, at least a certain number of bits will have been overwritten with the specified probability. Such a plot represents the upper tail area of the cumulative distribution of the values in Table 1. The alternate presentation is plotted below in Table 2. The significance of each legend in Table 2 is the same as in Table 1.
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1 2 3 4 5 6
-----------------------------------------------------------------
1 1 0 0 0 0 0
2 1 0.83333 0 0 0 0
3 1 0.97222 0.55556 0 0 0
4 1 0.99537 0.83333 0.27778 0 0
5 1 0.99923 0.94136 0.55556 0.09259 0
6 1 0.99987 0.97994 0.74846 0.24691 0.01543
7 1 0.99998 0.99323 0.86420 0.41409 0.05401
8 1 1 0.99773 0.92871 0.56413 0.11403
9 1 1 0.99924 0.96322 0.68566 0.18904
10 1 1 0.99975 0.98123 0.77818 0.27181
Table 2
Messerschmitt presents in equation 16 an expression for the mean value of the number of overwrites as a function of switch sections traversed.
Table 3 presents values obtained from equation 16 for several numbers of traversed switches:
switches mean number of
traversed bits overwritten
--------- ----------------
1 1
2 1.833
3 1.528
4 3.106
5 3.589
6 3.991
7 4.326
8 4.605
9 4.837
10 5.031
Table 3
4. NOTES
1. The actual delay (one way) required here is about 125  s minus the period of one bit (647.7 ns). Here, and elsewhere in this contribution, the single bit offset in the delay requirement will be ignored for simplicity.
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2. Both [6] and [7] specify a maximum delay based on route length of
0.0168 * M, where M is the facility length in miles and the result is in milliseconds.
5. REFERENCES
[1] ANSI T1.403.02-1999, Network and Customer Installation Interfaces
- DS1 Robbed-Bit Signaling State Definitions
[2] David G. Messerschmitt, Effect of Bit-Robbing in Tandem Digital
Switches, IEEE Transactions on Communications, Vol. COM-27, No. 7,
July, 1979
[3] ANSI T1.107-1995, American National Standard for Telecommuni- cations - Digital Hierarchy - Formats Specifications
[4] Working Group T1X1.3 contribution T1X1.3/2000-002R0, (draft)
Technical Report on Synchronization Architecture
[5] Working Group T1E1.2 contribution T1E1.2/2000-024, Digital Tandem
Channel Unit with U-DSL Interface
[6] Bellcore GR-499-CORE, Transport Systems Generic Requirements
(TSGR): Common Requirements, Issue 1, December, 1995
[7] ANSI T1.506-1997, American National Standard for Telecommuni- cations - Network Performance - Switched Exchange Access Network
Transmission Specifications
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