==============================
Chip Designer
December 17, 2007
Performance Challenges
www.chipdesignmag.com/chipdesigner
==============================
Please see below for address change or subscribe/unsubscribe instructions.
In this Issue:
1. E-DFM: The Future of Parametric Yield Success
2. Smallest 1GB DDR2 Memory Chip
3. Multi-Mode Multi-Corner Signal Integrity Solution for 65/45nm
4. New Draft Standard for Transaction-Level Modeling
5. Li-Ion/Li-Polymer Chargers with Auto USB or AC Power-Source
6. Taiwanese Company Releases 65nm DFM Design Enablement Kit
7. Multi-Standard Digital Terrestrial Radio in Cars
8. In-Depth Coverage Links
> Global Approach Could Enable Low-Energy Software-Defined Radios
> It's the Best Christmas Present Ever
9. Featured Book
> The Composition of Matter
10. Happenings -- Conferences
********************
1. Viewpoint - Exclusive
********************
E-DFM: The Future of Parametric Yield Success
Carey Robertson, Director of Product Marketing, Mentor Graphics
(http://www.mentor.com/)
[headshot: 1207_CD_CRobertson.JPG]
At 45nm, yields exhibit drastic drop-offs, and designs fail to consistently achieve their technical and
competitiveness objectives. As more and more features are placed into smaller and smaller spaces, the
unintended effects of this “crowding” are creating havoc with yield and performance. The tools we have
today simply aren’t designed to recognize and resolve these issues.
Many designers have started to recognize that this push into advanced nodes has exposed a hitherto
insignificant set of yield problems. Physical problems that cause catastrophic failures, such as bridging
faults, have always been the primary focus of verification efforts. At 45nm, designs are now also
exhibiting parametric yield failures. Parametric yield issues arise when process variation has not been
sufficiently characterized, such that a circuit may have achieved design closure through standard
methodologies, but the silicon performance does not match the simulation results. Both physical and
parametric yield failures have similar negative business implications, in that new circuit designs will fail
to meet performance expectations.
To combat yield failures, the semiconductor industry has started to deploy new tools and methodologies
commonly referred to as DFM (design for manufacturing). Most efforts have concentrated on
catastrophic failures, or physical DFM problems. Recently, there has been an increased emphasis on
parametric yield issues, or electrical DFM. Electrical DFM (E-DFM) is a set of new technologies and
methodologies that specifically help address the parametric performance modeling problems
encountered at smaller geometries.
How Does E-DFM Compare and Contrast with Today’s “physical” DFM?
Physical DFM, as defined by one major foundry, is the technology that identifies and corrects silicon
hotspots, the locations in a design where particle defects or process variation can create shorts and opens
that cause functional failures. Physical DFM also implements geometric yield improvement with
recommended rules. Physical DFM is an important technology, especially during the early stages of new
process development, when low functional yield is the primary obstacle to process qualification. The
next critical milestone in nanometer design is the creation and validation of transistor and interconnect
models that are accurate enough to ensure that predicted versus actual circuit performance supports
design objectives, reduced costs, and increased product functionality.
E-DFM is an evolution from basic, as-drawn physical parameter inputs to a combination of physically
modeled, as-manufactured parameters that are design- and context-specific. These parameters are then
applied to next-generation device and interconnect models. With increased knowledge of how process
variation impacts circuit performance, designers can optimally center a design on the risk-reward
spectrum, between an aggressive design for better competitive performance and a conservative design
that ensures high parametric yield, but leaves potential functionality and performance on the table.
Taken as a whole, these core E-DFM technologies provide the information designers require to improve
parametric yield prediction at 45nm.
Physical DFM technologies are familiar to manufacturing and CAD personnel responsible for ensuring
designs meet the basic requirements for manufacturability. In slight contrast, the knowledge that can be
gained from E-DFM methods is critical to designers and business managers who must ensure that
designs meet datasheet performance specifications and competitive yield targets. It is now accurate to
say that both physical and electrical DFM are necessary techniques for achieving high yield at advanced
process nodes.
There are many perspectives of E-DFM to be considered. Probably the most fundamental categorization
separates full custom development from place and route applications. For full custom applications, EDFM tools augment the experience, skills, and intuition of designers, while in place and route
applications, E-DFM tools help provide many of the required inputs for effective place and route tool
operation and optimization.
Interconnect and transistor modeling applications also show significant differences in infrastructure and
application. For interconnect, the primary challenge is extracting and defining the correct physical
model while also capturing (in a practical manner) the inherent variation of the process. Physical
modeling of manufacturing processes and process variation considerations change the inputs to the
interconnect extraction problem, but the interface between extraction and downstream analysis tools
remains relatively unchanged.
For transistor modeling, there are additional challenges. First, the physical characteristics of a transistor
model must be modeled in a general enough sense to accommodate relevant lithographic contour and
physical proximity effects. Additionally, multiple transistor proximity stress effects must be
parameterized for inclusion in SPICE models. Lastly, the statistical nature of 45nm transistor models
operation requires significant process characterization to account for increasingly non-linear effects.
Compared to the 90nm node, these challenges will require significantly upgraded SPICE models to
achieve similar yields at 45nm and 32nm technologies.
The business implications of E-DFM technology are relatively straightforward. Companies that use
advanced physical modeling to enhance the accuracy of their physical to electrical conversion models
will have a competitive advantage in time-to-market, design competitiveness, and product yields from a
parametric perspective. Stop-gap measures such as restrictive design rules are useful for some
applications, but anything that restricts design flexibility for some, but not for all designers, is not
sustainable in a competitive market.
While E-DFM technology is currently only for early adopters who can put together the pieces of the
puzzle for themselves, it is a rapidly growing segment of DFM technology that promises to turn today’s
nearly impossible technical and business challenges into tomorrow’s mature and commonplace
solutions.
Carey Robertson is a director of product marketing at Mentor Graphics overseeing the marketing
activities for layout versus schematic (LVS) and extraction products.
********
2. News
********
Smallest 1GB DDR2 Memory Chip
Micron Technology has announced production sampling of its new 1GB DDR2 device fabricated on
68nm DRAM process technology. The new process, coupled with Micron’s 6F^2 technology, has
enabled the smallest production 1GB DDR2 memory, with a die size of just 56mm^2. Mass production
of the new 68nm 1GB DDR2 products is expected to begin in early 2008, with DDR3 and other lowpower DRAM following in the second half of the year. The new advanced memory technology will be
targeted at server, mobile, and other computing applications, where the benefits of reduced die size,
faster speeds, and lower power consumption are most critical.
Micron Technology >> http://www.micron.com/
********
3. News
********
Multi-Mode Multi-Corner Signal Integrity Solution for 65/45nm
Mentor Graphics has announced new technology in its Olympus-SoC place-and-route product that
accelerates signal integrity closure and improves the reliability of manufactured silicon. The multicorner, multi-mode (MCMM) capability of Olympus’ static timing analysis engine concurrently
computes delay shift and glitch for any number of mode and corner scenarios in a single pass. The
Olympus-SoC product’s routing and optimization engines have been enhanced to help eliminate signalintegrity violations concurrently over all variation scenarios. The solution includes per clock, per corner,
and per mode timing window computation; incremental signal-integrity updates over mode and corners
concurrently during implementation; routing techniques; and signal-integrity bottleneck identification
for directed concurrent delta-delay, delta-slew, and glitch optimization.
Mentor Graphics >> http://www.mentor.com/
********
4. News
*******
New Draft Standard for Transaction-Level Modeling
The Open SystemC Initiative (OSCI) has announced the release of the new transaction-level modeling
(TLM) standard, TLM-2 draft 2. This standard enables model interoperability and reuse at the
transaction level, providing a framework for ESL design. Design at the transaction level lets users
develop system-on-chip (SoC) virtual prototypes to assist in architecture analysis and enable early
software development, before availability of structural-level models. Transaction-level models can be
reused in functional verification environments as a golden reference for validation of intellectual
property in the context of the system. The OSCI TLM-2 standard makes the development of
interoperable ESL tools possible and provides the framework needed for model exchange within
companies and across the IP supply chain.
The Open SystemC Initiative >> http://www.systemc.org/
********
5. News
********
Li-Ion/Li-Polymer Chargers with Auto USB or AC Power-Source
Microchip Technology has announced the MCP73837 and MCP73838 (MCP73837/8) dual-input, highcurrent Li-ion polymer charge-management controllers with automatic USB or AC adapter powersource selection. The single-cell, integrated chargers enable charge currents of up to 1A from an AC
power source, plus charging currents of up to 100mA or 500mA from a USB port. MCP73837/8-based
charger designs can automatically charge from a PC’s USB port when no AC power is available. When
powered from a USB port, the devices ensure compliance with USB power specifications and adjust
outputs accordingly. One charger design can support multiple power sources. On-chip safety features,
such as thermal regulation, cell-temperature monitoring, and charge-timers, minimize charger-related
system damage.
Microchip Technology >> http://www.microchip.com/
*****************
6. International News
*****************
Taiwanese Company Releases 65nm DFM Design Enablement Kit
UMC has released its 65nm design for manufacturing (DFM) support package. The DFM Design
Enablement Kit (DEK) encompasses all the models required by qualified model-based DFM tools that
support UMC’s 65nm process technology. The company collaborated with leading EDA vendors to
develop the DEK to provide a DFM solution for its 65nm customers. UMC’s DEK package consists of
65nm DFM solutions in three main areas: critical area analysis, chemical mechanical polishing, and
lithography simulation check. The package includes a GUI for setup of a DFM design database, with
application notes and qualification reports for design reference. The application notes demonstrate how
the tools can be deployed in various design flows.
UMC >> http://www.umc.com/
*****************
7. International News
*****************
Multi-Standard Digital Terrestrial Radio in Cars
Dutch company NXP Semiconductors has introduced a global multi-standard digital terrestrial radio
solution for high-quality analog and digital radio for in-car entertainment. The AM/FM car DSP, the
Nexperia PNX9525, uses a software-defined radio approach to effortlessly manage multiple frequency
streams and integrate with existing DSP-based analog radio in a very small footprint. The Nexperia
PNX9525 is a software programmable DRM and DAB platform that allows switching between the two
standards. The SAF355x incorporates the HD radio technology from iBiquity. NXP’s solution combines
the PNX9525 and the SAF355x, which can be integrated with existing DSP-based AM/FM platforms to
deliver a multi-standard digital terrestrial radio experience.
NXP Semiconductors >> http://www.nxp.com/
****************************
8. In-Depth Coverage Links
****************************
Together, the growing number of wireless standards and the quest for seamless connectivity are creating
a need for functional flexibility in future radios. To learn more, read Bart Van Poucke and Liesbet Van
der Perre's "Global Approach Could Enable Low-Energy Software-Defined Radios."
Chip Design Editorial Feature >> http://www.chipdesignmag.com/display.php?articleId=1676
Sand is pouring through the hourglass and time is racing by when it comes to buying Christmas presents,
but don't despair, because I know just the thing. To learn more, read Clive "Max" Maxfield's "It's the
Best Christmas Present Ever."
iDesign Editorial Feature >> http://www.chipdesignmag.com/display.php?articleId=1796
************************
9. Featured Book
************************
The Composition of Matter
By R. von Steiger (editor), G. Gloeckler (editor), and G.M. Mason (editor)
ISBN: 0387741836
Publisher: Springer
Part of the "Space Sciences Series of ISSI," this book consists of papers developed from a joint
ACE/ISSI symposium on the "Composition of Matter," honoring the occasion of Johannes Geiss's 80th
birthday. The symposium and its resultant papers explore new insights into the composition of solarsystem and galactic matter as well as fractionation processes affecting samples of matter that have been
brought about by recent space missions, ground-based studies, and theoretical advances. The book's
structure mirrors the five symposium sessions: linking primordial to solar composition, planetary
samples, solar sources and fractionation processes, and interstellar gas and cosmic rays. The editors have
included most of the overview and invited papers and many of the contributed ones.
Springer >> http://www.springer.com/
************************
10. Happenings -- Conferences
************************
21st Conference on VLSI Design and the 7th International Conference on Embedded Systems
Hyderabad International Convention Centre (HICC), Hyderabad, India
January 4-8, 2008
http://vlsiconference.com/vlsi2008/
13th Asia and South Pacific Design Automation Conference
COEX, Soeul, Korea
January 21-24, 2008
http://www.aspdac.com/aspdac2008/
ISSCC
San Francisco, CA
February 3-8, 2008
http://www.isscc.org/isscc/
DesignCon 2008
Santa Clara Convention Center, Santa Clara, CA
February 4-7, 2008
http://www.designcon.com/2008/
Parallel and Distributed Computing and Networks (PDCN 2008)
February 12-14, 2008
Congress Innsbruck, Innsbruck, Austria
http://www.iasted.org/conferences/home-597.html
DVCon 2008
DoubleTree Hotel, San Jose, CA
February 19-21, 2008
http://www.dvcon.org/
International Symposium on Field Programmable Gate Arrays
Monterey Beach Resort, Monterey, CA
February 24-26, 2008
http://www.ece.wisc.edu/~kati/fpga2008/
Design Automation & Test in Europe (DATE)
March 10-14, 2008
ICM, Munich, Germany
http://www.date-conference.com/
ISQED '08: The 9th Annual Symposium on Quality Electronic Design
March 17-19, 2008
DoubleTree Hotel, San Jose, CA
http://www.isqed.org/
System Level Interconnect Prediction (SLIP 2008)
Newcastle University, Newcastle. U.K.
April 5-6, 2008
http://www.sliponline.org/
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2008)
April 7-9, 2008
Montpellier Convention Centre, Le Corum, Montpellier, France
http://www.lirmm.fr/isvlsi2008/
International Symposium on Networks-on-Chip (NoCS 2008)
Newcastle University, Newcastle, U.K.
April 7-11, 2008
http://async.org.uk/nocs2008/
15th Annual Reconfigurable Architectures Workshop (RAW 2008)
Miami, FL
April 14-15, 2008
http://www.ece.lsu.edu/vaidy/raw/
International Symposium on Physical Design (ISPD 2008)
Embassy Suites, Portland, OR
April 13-16, 2008
http://www.ispd.cc/
COOLChips XI
April 16-18, 2008
Yokohama Joho Bunka Center, Yokohama, Japan
http://www.coolchips.org/
International Symposium on VLSI Technology, Systems, and Applications
April 21-23, 2008
Ambassador Hotel, Hsinchu, Taiwan
http://vlsitsa.itri.org.tw/2008/General/
International Symposium on VLSI Design, Automation & Test
April 23-25, 2008
Ambassador Hotel, Hsinchu, Taiwan
http://vlsidat.itri.org.tw/2008/General/
Great Lakes Symposium on VLSI (GLSVLSI)
May 4-6, 2008
Orlando, FL
http://www.glsvlsi.org/
International Symposium on Circuits and Systems (ISCAS 2008)
Sheraton Seattle Hotel, Seattle, WA
May 18-21, 2008
http://www.iscas2008.org/
Semicon West
Moscone Center, San Francisco, CA
July 15-17, 2008
http://semiconwest.semi.org/index.htm
Signal and Image Processing (SIP 2008)
Kailua-Kona, HI
August 18-20, 2008
http://www.iasted.org/conferences/ipc-623.html
Circuits and Systems (CS 2008)
Kailua-Kona, HI
August 18-20, 2008
http://www.iasted.org/conferences/ipc-625.html
Intel Developer Forum
Moscone Center West, San Francisco, CA
August 19-20, 2008
http://www.intel.com/idf/index.htm
Read past issues of Chip Designer e-Newsletter:
http://www.chipdesignmag.com
CHIP DESIGNER e-NEWSLETTER CONTACTS
====================================================
Editor: Nicole Freeman
mailto:nfreeman@extensionmedia.com
Editorial Director: John Blyler
mailto:jblyler@extensionmedia.com
Advertising/Sponsorship Opportunities: Karen Popp
mailto:kpopp@extensionmedia.com
====================================================
To subscribe send a blank email to:
To unsubscribe send a blank email to:
ExtensionMedia's homepage:
http://www.extensionmedia.com/
====================================
Copyright 2007 ExtensionMedia Inc. All rights reserved.