Course Syllabus
ECE 623 – Diagnosis and Reliable Design of Digital Systems
Department:
Course Number:
Course Title:
Credit Units:
Electrical and Computer Engineering
ECE 623
Diagnosis and Reliable Design of Digital Systems
3
Course Description
Basic theory, techniques for testing digital circuits and systems. Design techniques for fault
tolerant and early diagnosable systems. Test generation for combinational and sequential logic
circuits, checking experiments. Gate level fault simulation, and its application to diagnosis.
Design techniques using static and dynamic redundancy for reliable systems. Design for
testability (DFT) including full and partial internal scan and boundary Scan. Memory test, delay
test and at speed testing. Built In Self Test (LBIST, MBIST). Reliability basics its relation
toaccelerated testing.
Prerequisites
Students taking this course should understand the material in ECE 620 or consent of the
instructor.
Texts and References
Required Text:
Ref Text:
Lecture Notes, Journal Papers
M.A.Breuer, A.D.Friedman and M.Abramovic
"DIGITAL SYSTEM TESTING AND TESTABLE DESIGN"
COMPUTER SCIENCE PRESS.
A list of references is also attached together with a list of journal papers on
individual topics.
Supplements:
Course handouts and supplementary materials will be distributed in the classroom.
Term Project:
a) Implementing D-algorithm, FAN or Podem algorithm
using a language of your choice.
b) Term paper ( for a list of topics consult the instructor).
Note:
* Homework solutions will be handed out.
* Besides textbook and lecture notes, there will
be some papers available from different journals.
* Exams are closed book, notes, etc.
* Final exam is comprehensive.
* Grading is based on +/- system
Topics Covered/Course Outline
I.
Introduction to testing
A.Basic Concepts
 Diagnosis
 Reliability
 Fault Tolerance
B. Fault Models
II.
Combinational circuit test generation
A.Truth Table Methods
B. Algebraic Methods
 Boolean Difference
C. Path Sensitization Methods (Algorithmic test procedures)
 D-algorithm
-FAN, PODEM Algorithm
 Critical path Test
III.
Fault Collapsing
A. Fault Equivalence and Dominance
B. Multiple Faults
C. Special Circuits
IV.
Test Generation for Sequential Circuits
V.
Functional Testing of Sequential Circuits
A. Checking Sequences and Machine Identification
B. Path Sensitization Methods
C. Asynchronous Circuits
D. Delay Faults and Hazards
VI.
PODEM Algorithm for Combinational Circuits Test
VII. Fault Simulation
A. Fault Simulation for Combinational Circuits
B. Fault Simulation for Sequential Circuits
VIII. Random Testing
A. Comparison Testing
B. Hybrid Testing
IX. Test Compaction
Transition Count Test
Linear Feedback Shift Register (LFSR) Testing
X.
Design For Testability(DFT)
Testable circuits
 Readily testable
 Self-checking
 Self – testing
_ SCAN TEST
-Partial Scan
-Full Scan
XI.
Memory Testing
XII.
BUILT-IN SELF-TEST TECHNIQUES (BIST)
A. Test Pattern Generation For BIST
B. Generic Off-line BIST Architectures
C. Specific BIST Architectures
D. MBIST, LBIST
E. Conclusion
XIII. Fault Tolerant Digital Systems
A. Measure of fault tolerance
B. Reliability, MTBF, MTBR, MTTF
C. Redundancy techniques (TMR)
D. Fault tolerant systems
 Dual System
 Space borne computers
XIV. Accelerated Test
-Temperature Stress Test (Burn-In, Temperature Cycling).
-Voltage stress test.
-Electro Static Discharge (ESD) test.
ASSESSMENT METHODS
Midterm examinations, homework assignments, term project and final exam.
Design projects are based on individual and/or teamwork depending on the scope of
the project selected and must be formally presented by the students in class.
Course Objectives
After completing this course the students should be able to:
1. Understand advanced digital testing algorithms.
2. Use the appropriate test algorithm methods for achieving digital certain fault coverage
specifications in design.
3. Understand design for testability (DFT) techniques as it applies to digital design.
Become familiar with how to optimize a test plan based on a given reliability (fault
coverage.
4. Use the fault tolerant methods to increase the reliability (fault tolerance) for system
design.
5. Understand the fundamentals of reliability concepts, accelerated tests such as burn-in,
temp cycling and HAST.
6. Understand different techniques in Built In Self Test (BIST) such as MBIST and
LBIST.
7.
Understand and apply test techniques such as Iddq test, at speed test and delay tests.
Relationships to Program Outcomes
This course supports the achievement of the following outcomes:
a) Ability to apply knowledge of advanced principles to the analysis of electrical and
computer engineering problems.
b) Ability to apply knowledge of advanced techniques to testing of design systems.
c) Ability to apply the appropriate design practices, emerging technologies, state-of-the-art
design techniques, software tools, and research methods for design and design for
testability of digital systems.
d) Ability to use the appropriate state-of-the-art engineering references and resources,
including IEEE test journals and industry publications, needed to find the best solutions
to system design.
e) Ability to communicate clearly and use the appropriate medium, including written, oral,
and electronic methods.
f)
Ability to maintain life-long learning and continue to be motivated to learn new
subjects.
g) Ability to learn new subjects that are required to solve problems in industry without
being dependent on a classroom environment.
h) Ability to be competitive in the engineering job market or be admitted to an excellent
Ph.D. program.
References:
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Agrawal, V.D. and Seth, S.C., Test generation for VLSI chips, IEEE Computer Society Press, 1988.
Butler, Kenneth M., Assessing Fault Model and Test Quality, Kluwer Academic Publishers, 1992
Cheng, K.T. and Agrawal, V.D., Unified Methods for VLSI Simulation and Test Generation, Kluwer
Academic Publishers, 1989.
Eichelberger, Edward B., ed., Structured Logic Testing, Prentice Hall, 1991
Fujiwara, Hideo, Logic Testing and Design for Testability, MIT Press, 1985
Hnatek, Eugene R., Digital Integrated Circuit Testing from a Quality Perpective (New York: Van
Nostrand Reinhold, 1993)
Miczo, Alexander, Digital Logic Testing and Simulation, Harper & Row, 1986
Rajsuman, Rochit, Digital Hardware Testing (Boston: Artech House, 1992)
Tsui, Frank, LSI/VLSI Testability Design, McGraw-Hill, New York, 1987
Wang, Francis, Digital Circuit Testing (San Diego: Academic Press, 1991)
Boundary Scan Testing
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Bleeker, Harry, van den Eijden, Peter, de Jong, Frans, Boundary Scan Test. A Practical Approach,
Kluwer Academic Publishers, 1993, ISBN 0-7623-9296-5
Maunder, Colin, The Board Designer’s Guide to Testable Logic Circuits, Addison-Wesley, 1991,
ISBN 0-201-56513-7
Built-In Self Test (BIST)
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Bardell, P.H., McAnney, W.H., Savir, J., Built-In Test for VLSI: Pseudorandom Techniques, Wiley
Interscience, 1987
Goessel, M., Graf, S., Error Detection Circuits, McGraw-Hill, ISBN 0-07-707438-6
IDDQ Testing
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The Journal of Electronic Testing (JETTA), Vol.3, No.4, Dec. 1992 (Special Issue devoted to IDDQ
testing with good tutorial material and the most recent papers.)
Gulati, Ravi, et.al., IDDQ Testing of VLSI Circuits, hardcover version of the JETTA issue, Kluwer
Academic Publishers.
Maliya, Y. and Rajsuman, R., Bridging Faults and IDDQ Testing, IEEE Computer Society Press
Technology Series (Order number 3215-05), Library of Congress Number 92-30950, IEEE Catalog
number EH0357-4, ISBN 0-8186-3215-1
Memory Testing
 Van de Goor, A., Testing Semiconductor Memories, Willey, ISBN 0-471-92586-1
System Testing
 Simpson, William R., and Sheppard, W., System Test and Diagnosis, Kluwer Academic Publishers,
1994, ISBN 0-7923-9475-5
Test Integration
 Parker, Kenneth, Integrating Design and Test: Using CAE tools for ATE Programming, IEEE order
number EH0261-8, IEEE Service Center
Transistor Level Modeling
 Rajsuman, R., Digital Hardware Testing, Transistor-Level Fault Modeling and Testing, Artech
House, ISBN 0-89006-580-2
 Magazine: IEEE Design and Test, IEEE Computer Society
 Industry-oriented periodical: Test & Measurement World
 Conference Proceedings
 International Test Conference (ITC) , IEEE.
 International Conference on CAD (IEEE/ACM)
 Design Automation Conference (ACM/IEEE)
Prepared by:
Prof. Ramin Roosta