Glitch filtering in gate level power estimation using dual-transition
probability
Fei Hu
Abstract
Most of existing gate-level probabilistic approaches on power estimation fails to model glitch
filtering effect accurately. However, this effect could have significant impact on the power
dissipation in a circuit and therefore not negligible. In this paper, we propose an accurate glitch
filtering method which can be applied to existing probability simulation and tagged probability
simulation techniques. Our glitch filtering method is based the new measure of dual-transition
probability that captures the probability of states on one node at two different time instance.
Experiments show that the application to the tagged probability simulation gives a power estimation
which has a more stable performance than that of the original one. For certain circuits with a large
component of glitch power, up to 28% estimation accuracy improvements have been obtained.
1. Introduction
Power estimation refers to the techniques that can estimate or predict the average power and
maximum power for a given circuit. It’s been well understood that accurate power estimation
methods are critical to IC designs because the power consumptions for each module must meet
the specification during the design phase. Otherwise, a costly redesign process is inevitable.
Numerous computer aided design tools for power estimation has been developed to address this
issue. From the interest of estimation and circuit details provided, power estimation techniques
ranges from circuit level SPICE simulation to high level estimation of power dissipation of a
CPU.
For gate level power estimation, a gate level netlist of the circuit is provided. The power
components that consist of the total power dissipation for a CMOS circuit are switching power
( Pswitching , caused by the signal transitions charging and discharging load capacitors), leakage
power ( Pleakage , caused by sub-threshold current of transistors when no input changes) and
short-circuit power ( Pshort  circuit , power dissipation during the gate switching, when both PMOS
and NMOS network are turned on) [2]. Among these three components, switching power has been
the dominant component in the past decades. Pswitching  kCLVdd2 f clk , where k is the switching
activity factor, C L is the load capacitance, Vdd is the supply voltage and f clk is the clock
frequency. Although leakage power is becoming more and more significant as the device size
keeps shrinking, an accurate estimation of switching power is always of great interests.
Switching power estimation at gate level normally has two approaches, simulation-based and
probabilistic methods. Power consumption at each node can be calculated from the switch
activity and load capacitance of the node. Although the event-driven logic simulation can give
the precise switching activity at each node, the major drawback is that a large number of typical
input vectors have to be simulated in order to get a meaningful average power. Therefore, it is
normally very slow and strongly input pattern dependent. On the other hand, probabilistic
methods only require one analysis to derive the power given input probabilities and are more
preferred.1 Previous probabilistic approaches differ in terms of delay model used, the way to
handle spatial temporal independence, and glitch filtering effect considerations. They also vary
on the estimation complexity and speed.
Most of early probabilistic approach for power estimation [3,5,11,9,10] are under zero delay
assumption, which means only steady state signal values are analyzed. Premature signal
transitions during the transient stage, so called glitches or hazards, can not be analyzed by
zero-delay models. In reality, power consumed by glitches is not negligible in most cases and
some of the late works tried to include the glitch power for a more accurate estimation. In
[12], works in [10] has been extended into real delay case. There are many other approaches
based on real delay model or differential delay to account for glitch power. Probabilistic
simulation (CREST) [1,6,7] and Tagged probability simulation [13,4] was proposed to
propagate probability waveform throughout the circuit. Transition density approach, proposed
by Najm [8], utilize a differential delay model (assuming no two signal will arrive at a gate at
the exactly same time) to include glitch power into the total switching power. For most of
these techniques, except Tagged probability simulation, glitch filtering effect are not
considered. Glitch filtering effect refers to the fact that glitches with pulse width less than the
inertial delay of the gate will not be able to propagate to the output of the gate. The glitch
filtering effect can change the switching activity of a gate significantly especially for gate
with a large inertial delay. As far as we know, no one has proposed an accurate method to
account for this effect. Even in tagged probability simulation, where glitch filtering is
considered, the filtering is so approximated that glitches coming from single input will not be
filtered.
In this paper, we propose an accurate glitch filtering method based on probability simulation
approaches. Our technique can be applied to both probability simulation (CREST) and tagged
probability simulation. Since probability simulation assumes spatial independence of input signals,
it leads to a larger estimation error when the circuit contains reconvergent fanouts. Our application
to the tagged probability waveform shows significant improvements in estimation accuracy for
some circuits with a large component of glitch power. The organization of this paper is as follows.
In section 2, we will briefly introduce the background of probability simulation and related terms.
In section 3, we will discuss the way to propagate probability waveform throughout the circuit. In
section 4, the new glitch filtering will be discussed. We will show some experimental result in
section 5 and draw our conclusions and future works in section 6.
1
Probabilistic methods are also pattern dependent because analysis results depends on supplied
probabilities. However, no specific input pattern is required for probabilistic methods and therefore it is
less pattern-dependent.
2. Backgrounds
Our new glitch filtering method is based on previous technique of probability simulation.
Here we have an introduction on probability waveform and Tagged probability waveform.
A. PROBABILITY WAVEFORM
Probability waveforms [7] represent the logic waveforms of each node collectively using
probabilistic measurements. A probability waveform is a sequence of transitions edges over
time where each edge is annotated with a probability of occurrence. In a probability
waveform w, two concepts are critical, signal probability and transition probability. Signal
probability spn (t ) is defined as the probability of node n having logic one at time t.
Transition probability refers to the probability of signal transition at the node. More precisely,
the probability of an event that signal value of node n transfer from zero to one (or one to zero)
at time t can be defined as a rising transition probability tun (t ) (or falling transition
probability td n ( t ) ). The probability waveform of a node is a compact representation of all
possible waveform at that node under the input stimuli and can be constructed easily if we
enumerate all possible logic waveform and corresponding occurrence probability. A
probability waveform can be represented by an initial signal probability followed by a
sequence of transition probabilities in the temporal order. E.g.
w  {spn (0), tun (t0 ), td n (t0 ),..., tun (tk ), td n (tk )} .
Note that spn (t  )  spn (t )  tun (t )  td n (t ) .
In this paper, probability waveform is the representation of logic waveforms within a single
clock period. We also extend the definition of transition probability to general cases. We
define transition probability Pnsn (t ) as the probability that node n has a logic transition state
sn ( sn {00,01,10,11} ) at time t. Therefore, tun (t )  Pn01 (t ) and tdn (t )  Pn10 (t ) . Pn11 (t ) (or
Pn00 (t ) ) denote the probability of node n hold on logic one (or zero) at time t. Consequently,
we have spn (t )  Pn10 (t )  Pn11 (t ) and spn (t )  Pn11 (t )  Pn01 (t ) . The switching power
dissipation of a node can be described as
Pav (n) 
1
f clkVdd2 Cn  ( Pn01 (ti )  Pn10 (ti ))
2
(1)
, where Cn is the load capacitance of node n and tun (ti )  td n (ti ) is the transition density of
the node.
B. TAGGED PROBABILITY WAVEFORM
A tagged probability waveform [4] can be viewed as a partitioning of a probability waveform
according to the initial and final steady state signal values of each logic waveform contributed
to it. That is, if we enumerate all possible logic waveform for a node, logic waveform with
same steady state values are to be grouped to form one probability waveform, which is then
tagged with the steady state values. Four tagged probability waveform can be defined to a
11
node n: wn00 , wn01 , w10
n , and wn , where 00, 01, 10, 11 are tags. Similar to probability
waveform, spnxy (t ) ( x, y {0,1} ) represents the signal probability in tagged probability
waveform wnxy . More accurately, spnxy (t ) represents the probability that node n has logic
one at time t and its initial and final steady state values are x and y. Furthermore, tunxy (t )
(or td nxy (t ) ) represent the rising (or falling) transition probability in tagged probability
waveform wnxy . That is the probability that node n has a zero to one (or one to zero) transition
at time t and its steady state values are x and y. Note that either spnxy (t ) , tunxy (t ) , or tunxy (t )
are not conditional probabilities. A simple summation of four tagged probability waveform
can reconstruct the original probability waveform. Tagged waveform probability, denoted as
P( wnxy ) , is also defined, which is the sum of occurrence probabilities of all logic waveforms represented
by wnxy . Figure 1 shows an example of probability waveform and tagged probability
waveform. Each tagged probability waveform is labeled with its tag and the
corresponding P( wnxy ) .
Similar to probability waveform, we extend the definition of transition probability in tagged
probability waveform to a more general form. We define transition probability in tagged
waveform Pnsn, xy (t ) as the probability that node n has a logic transition state sn
( sn {00,01,10,11} ) at time t and its initial and final steady state values are x and y
( x, y {0,1} ).The switching power dissipation of a node can be described as
Pav (n) 
1
f clkVdd2 Cn  ( Pn01, xy (ti )  Pn10, xy (ti ))
2
i
x
y
, where Cn is the load capacitance of node n and
density of the node.
( P
01
n , xy
x
(2)
(ti )  Pn10, xy (ti )) is the transition
y
11 sp
1
P=0.2
0
1
0.35
0.15
0.15
P=0.15
0
1
t1
t2
01 sp
P=0.05
0
1
P=0.05
0
1
0.15
P=0.35
0
t2
t1
0.05
0.1
t1
P=0.1
0
1
t2
t
10 sp
t
0.15
(a)
0.05
0.1
t1
sp
t
P=0.1
0
1
0.1
0.1
00 sp
0.2
0.2
0.35
t2
t
t2
t
0.5
t1
t2
(b)
t
t1
(c)
Figure 1. A example of probability waveform and tagged probability waveform. (a) shows all possible logic
waveform within one clock period for a given node and corresponding occurrence probabilities. (b) shows a
probability waveform constructed from (a), the y axis is the signal probability. Arrows are rising edges and falling
edges which are annotated with its transition probability. (c) shows four tagged probability waveforms constructed
from (a), and each waveform is labeled with its tag (00,01,10,or 11). The y axis is the signal probability and the
height of dashed line indicate the tagged waveform probability P( wnxy ) .
3. Propagation of waveform
The waveform propagation scheme in probability waveform and tagged probability waveform is
similar. However, for tagged probability waveform four waveforms are propagated through the
circuit. Also the propagation of single probability waveform is simpler because no spatial
correlation is considered.
A. PROPAGATION OF PROBABILITY WAVEFORM
For probability waveform, the spatial correlation between two different inputs is ignored and the
waveform will not be exact when circuits contain reconvegent fanout. For a two input AND gate,
with inputs a, b and output c. The output probability waveform at node c is calculated as
tuc (t  d )  Pc01 (t  d )  Pa01 (t )Pb11 (t )  Pa01 (t )Pb01 (t )  Pa11 (t )Pb01 (t )
(3)
tdc (t  d )  Pc10 (t  d )  Pa10 (t )Pb11 (t )  Pa10 (t )Pb10 (t )  Pa11 (t )Pb10 (t )
(4)
, where d is the inertial delay of the AND gate. An OR gate is similar to a AND gate with
Pa11 (t ), Pb11 (t ) be substituted by Pa00 (t ), Pb00 (t ) in above equations. In our implementation, to
limit the complexity, gates with two or more inputs will be decomposed to two input gates first
then perform the waveform propagation. To propagate the waveform, an initial signal probability
spn (0 ) is necessary for each node n. spn (0 ) is the steady state signal probability that can be
derived from primary input using global OBDD approach [9]. In practice, we can use a zero delay
bit-parallel logic simulator to find out the values [4].
B.
PROPAGATION OF TAGGED PROBABILITY WAVEFORM
The propagation of tagged probability waveform is more complex because each input has four
waveforms. In tagged waveform propagation, circuits with tree structure and circuits with
reconvergent fanouts are handled differently. For circuit with tree structure, signal connected to
two inputs of the AND gate are uncorrelated if the circuit inputs are uncorrelated. Therefore, the
transition probability for a two input AND gate can be calculated as
tucxy ,wz (t  d )  Pc01,( xy ,wz ) (t  d )  Pa01, xy (t ) Pb11,wz (t )  Pa01, xy (t ) Pb01,wz (t )  Pa11, xy (t ) Pb01,wz (t )
(5)
td cxy ,wz (t  d )  Pc10,( xy ,wz ) (t  d )  Pa10, xy (t ) Pb11,wz (t )  Pa10, xy (t ) Pb10,wz (t )  Pa11, xy (t ) Pb10,wz (t )
(6)
, where a, b are the inputs, c is the outputs, x, y, w, z {0,1} . The left terms of each equation is
the joint-tagged (by xy,wz) transition probability. Since each joint tag actually indicates the initial
and final steady state value of logic waveform for each input, we can easily calculate the initial
and final steady state value of logic waveform at the output, which will be the output tag. All
joint-tagged waveforms with same output tag are added together. After this procedure, 16
joint-tagged waveforms are combined to form 4 tagged waveforms. And these 4 waveforms will
be propagated to the fanout gates. As in probability simulation, An OR gate is similar to a AND
gate with Pa11, xy (t ), Pb11,wz (t ) be substituted by Pa00, xy (t ), Pb00,wz (t ) in above equations. Gates with two
or more inputs will be decomposed to two input gates to avoid the complexity.
For circuits with reconvergent fanout, spatial correlations of signals are not negligible. As
illustrated in [4], exact calculation of transition probability is very difficult. To exactly
calculate the output waveform from two input waveform of a two input gate, we need to know
the correlation between any two states of different inputs at the same time instance. Therefore,
the macroscopic correlations between steady state signal values (tags) are used to
approximate the exact correlations. The macroscopic correlation are encapsulated by
correlation coefficients, which is defined, for tagged waveform waxy , wbwz ,
axy,b,wz 
P( waxy ^ wbwz )
P( waxy ) P( wbwz )
(7)
,where x, y, w, z {0,1} . The correlation coefficient is the ratio of the probability of both
tagged waveform occurs and the product of individual tagged waveform probability.
Under the assumption that all correlations between any two states of different inputs at the
same time instance are the same as axy,b,wz , the transition probabilities for a two input AND
gates can be calculated as
tucxy ,wz (t  d )  Pc01,( xy ,wz ) (t  d )  ( Pa01, xy (t ) Pb11,wz (t )  Pa01, xy (t ) Pb01,wz (t )  Pa11, xy (t ) Pb01,wz (t ))axy,b,wz (8)
td cxy ,wz (t  d )  Pc10,( xy ,wz ) (t  d )  ( Pa10, xy (t ) Pb11,wz (t )  Pa10, xy (t ) Pb10,wz (t )  Pa11, xy (t ) Pb10,wz (t ))axy,b,wz (9)
, where a, b are the inputs, c is the outputs, x, y, w, z {0,1} . The rest of the propagation is
the same as the case with tree structure circuit.
4. New Glitch filtering Method
The glitch filtering effect refers to subtraction of transition probabilities from probability
waveforms. In tagged probability simulation [4], glitch filtering on joint-tagged waveform
wcxy ,wz of a two input AND gate with inertial delay d can be described as follows. For a rising
transition event tuaxy (t1 ) , all of the falling transition events tudwz (t2 ) that comes from the other
gate input with t1  t2  t1  d are subject to glitch filter. It means that axy,b,wz tuaxy (t1 )td bwz (t2 ) is
subtracted from both tucxy ,wz (t1  d ) and tdcxy ,wz (t2  d ) . In essence, they assume that tuaxy (t1 )
and tudwz (t2 ) are also correlated by macroscopic correlations, described by axy,b,wz .
axy,b,wz tuaxy (t1 )td bwz (t2 ) represents the probability that both rising and falling transitions happens at
the output c at time t1,t2, which is subjected to the filtering since the pulse width is less than d.
This process is applied to each joint-tagged probability waveform before they merged into four
output tagged probability waveform. For multiply input gates, only the last gate in the
decomposed network is subject to glitch filtering.
A. DUAL-TRANSITION PROBABILITY
The above method for glitch filtering is very imprecise. First of all, the glitch coming from the
single input can not be filtered by this method. 2nd, even if we maintain the same assumption for
the use of macroscopic correlation, the probability that both rising and falling transitions happens
at t1, t2 is not simply axy,b,wz tuaxy (t1 )td bwz (t2 ) . In probability waveform, either a or b (inputs of the
AND gate) could has four possible states at t1 (or t2 ), a rising transition (01), a falling transition
(10), holding on one (11), or holding on zero (00). To have a rising transition on the output c at
t1 +d, three possible combinations of states of a and b at t1 are (01, 01), (01, 11) or (11, 01).
Similarly, to have a falling transition on the output c at t2+d, three possible combinations of
states of a and b at t2 are (10, 10), (10, 11) or (11, 10). To have an accurate estimation of the
probability that both transition happens at the output, joint probability of events at t1 and t2 on
each input should be adopted.
For our new glitch filtering method, we define dual-transition probability Pnsn, xy1,sn 2 (t1 , t2 ) as the
joint probability that node n has the state sn1 at time t1 and the state sn2 at t2 on the xy tagged
probability waveform, where sn1, sn2 {00,01,10,11} and x, y {0,1} . Then, the probability
that both rising and falling transition happens at t1, t2 on the output of a two input AND gate can
be calculated as
3
3
i
Pc01,10
,( xy , wz ) (t1  d , t2  d )   Pa , xy
i 1 j 1
sa1 , sa 2 j
sb1 , sb 2 j
(t1 , t2 ) Pb,wzi
(t1 , t2 )axy,b,wz
(10)
, where c is the output, a, b is the inputs, d is the inertial delay of the gate, x, y, w, z {0,1} ,
( sa1i , sb1i )  {(01,11), (11,01), (01,01)} , and ( sa 2 j , sb2 j ) {(10,11), (11,10), (10,10)} .
Note that we still adopted the macroscopic correlation axy,b,wz to approximate the spatial
correlation between two inputs. The output dual-transition probability is joint-tagged with
(xy,wz). Similar to the merging of joint-tagged transition probabilities, joint-tagged
dual-transition probabilities are added together according to its output tag to form the (single
tagged) dual-transition probability.
B. NEW GLITCH FILTERING
With the new notion of dual-transition probability, the glitch filtering on joint-tagged
waveform wcxy ,wz of a two input AND gate with inertial delay d is modified as follows. For a
rising transition event at t1, all falling transition events at t2 that has t1  t2  t1  d are subject
to glitch filter. It means that the dual-transition probability Pc01,10
,( xy , wz ) (t1 , t2 ) is subtracted from
xy ,wz
xy , wz
both tuc (t1  d ) and tdc (t2  d ) . Moreover, For a falling transition event at t1, all rising
transition events at t2 that has t1  t2  t1  d are subject to glitch filter. The dual-transition
xy ,wz
probability Pc10,01
(t1  d ) and tucxy ,wz (t2  d ) . This
,( xy , wz ) (t1 , t2 ) is subtracted from both td c
process is applied to each joint-tagged probability waveform before they merged into four output
tagged probability waveform. Figure 2 shows an example of the process.
wa11
sp
0.5
0.2
sp
0.2
a
t1 t2
wb11
c
t
0.5
0.2
0.06 0.1
0.1 0.06
t1' t2' t3' t
d
b
sp
wc11 0.25
0.2
t 2 t3
t
Glitch filtering
10,01
11,11
Pc10,01
,11 ( t1 ', t2 ')  Pa ,11 ( t1 ', t2 ') Pb ,11 ( t1 ', t2 ')  0...  0  0.2 *0.3  0.06
10,01
11,11
Pc10,01
,11 ( t2 ', t3 ')  Pb ,11 ( t2 ', t3 ') Pa ,11 ( t2 ', t3 ')  0...  0  0.2 *0.3  0.06
10,11
11,01
Pc10,01
,11 ( t1 ', t3 ')  Pa ,11 ( t1 ', t3 ') Pb ,11 ( t1 ', t3 ')  0...  0  0.2 *0.2  0.04
sp
wc11 0.25
t1' t2' t3' t
Figure 2 An example of the glitch filtering process. Propagation of
probability waveform for a two input AND gate with an inertial delay d is
shown. For glitch filtering, we assume all t1<t2<t3<t1+d
C. PROPAGATION OF DUAL-TRANSITION PROBABLITY
Dual-transition probability is propagated from the primary inputs throughout the circuit. The
general equation for propagation of dual-transition probability is as follows,
k
l
Pcs,(1,xys 2,wz ) (t1  d , t2  d )   Pa , xyi
sa1 , sa 2 j
i 1 j 1
sb1 , sb 2 j
(t1 , t2 ) Pb,wzi
(t1 , t2 )axy,b,wz
(11)
where c is the output, a, b is the inputs, d is the inertial delay of the gate, x, y, w, z {0,1} ,
( sa1i , sb1i )  Q1 , and ( sa 2 j , sb2 j )  Q 2 . Q1(or Q2) represents the group of input combinations
on a and b that give output state s1 (or s2) and the size of Q1(or Q2) is k (or l). For primary
inputs, where transition can only occur at time 0, Pns,1,xys 2 (0, t )  Pns,1xy (0) or Pns,1,xys 2 (0, t )  0
depending on the value of s1 and s2.
It is important to update values of dual-transition probability after the glitch filtering. Indeed,
no two transitions could happen with a time difference less than the gate delay d. The
dual-transition probability is updated as follows. Define s2[1], s2[2] as the first (left) and 2nd
(right) bit of s2. For t1, t2 with t1  t2  t1  d , Pns,1,xys 2 (t1 , t2 )  Pns,1xy (t1 ) if s2[1]  s2[2]  s1[2]
and Pns,1,xys 2 (t1 , t2 )  Pns,2xy (t2 ) if s1[1]  s1[2]  s2[1] . Otherwise, Pns,1,xys 2 (t1 , t2 )  0 .
To help update dual-transition probability for t1, t2 with t1  d  t2 , we define dual-transition
correlation coefficient ns1,, xys 2 (t1 , t2 ) as follow,
ns1,, xys 2 (t1 , t2 ) 
Pns,1,xys 2 (t1 , t2 )
Pns,1xy (t1 ) Pns,2xy (t2 )
(12)
, where s1, s2 {00,01,10,11} , x, y {0,1} . Pns,1,xys 2 (t1 , t2 ) is the dual-transition probability and
Pns,1xy (t1 ) is the transition probability on tagged waveform. Before the glitch filtering is applied,
ns1,, xys 2 (t1 , t2 ) ’s are calculated. After the glitch filtering, we assume the correlation for transitions
at t1, t2 with t1  d  t 2 does not change, and update dual-transition probability as follows,
Pns,1,xys 2 (t1 , t2 )  Pns,1xy (t1 ) Pns,2xy (t2 )ns1,, xys 2 (t1 , t2 )
(13)
Note that Pns,1xy (t1 ), Pns,2xy (t2 ) here is the new transition probability after the subtraction. To avoid
the exponential increase of complexity, only correlation coefficients (and dual-transition
probabilities) with t2-t1<dmax are propagated, where dmax is the maximum gate delay of the
circuit.
5. Experimental Results
Although we explained our new glitch filtering method under tagged probability simulation. Our
glitch filtering method can be applied to both probability simulation and tagged probability
simulation. The proposed algorithm has been implemented in software prototypes which are to be
referred to as “ProSim + NEW” and “TPS + NEW”. The software takes a description of a circuit
and gives the estimation of switching power (in terms of transition density) at each node. The
description of circuit includes the netlist of the circuit and input signal probabilities. In our
experiments, spatial and temporal independence is assumed for primary inputs. Input signal
probabilities for PIs are 0.5 and we randomly generate 40,000 input vectors under the same
probability as the input sequence for the logic simulator. As that in [4], the transition probabilities
and macroscopic correlations for steady state signals are first generated using a zero delay logic
simulator and then fed into our power estimation software.
Our first experiment is a simple tree structure circuit as shown in Figure 3. Gates are given
randomly selected delay values. Results are compared in table 1. The power estimates (in terms of
transition density) for each node from different probability simulations are compared against those
obtained from logic simulation over the entire vector sequence. The percentage error is the ratio
between the absolute error and the average node activity. We can see our new glitch filtering
method gives a very accurate estimation in both cases. On the other hand, TPS itself gives a larger
error because of the inaccurate glitch filtering at node 31. Note that for a tree structure circuit, no
spatial correlation exists in the circuit if signal at PIs are independent. Therefore, probability
simulation can perform well in this case.
1
1
17
2
1
3
18
3
4
25
29
1
26
3
5
1
6
19
3
20
7
4
31
8
3
9
1
10
21
32
2
22
11
12
5
27
28
13
14
1
23
2
24
15
16
2
3
30
1
33
Figure 3 A tree structure circuit
Node
Logic
ProSim + NEW
Tagged ProSim (TPS)
TPS + NEW
transition
transition
transition
transition
density
density
Simulator
Total
Abs error
density
Abs error
density
Abs error
17
0.45701
0.4608
0.80%
0.460576
0.75%
0.460576
0.78%
18
0.45991
0.4608
0.19%
0.460277
0.08%
0.460277
0.08%
19
0.46043
0.4608
0.08%
0.46039
0.01%
0.46039
0.01%
20
0.46193
0.4608
0.24%
0.460373
0.33%
0.460373
0.34%
21
0.46222
0.4608
0.30%
0.460688
0.32%
0.460688
0.33%
22
0.46184
0.4608
0.22%
0.460396
0.30%
0.460396
0.31%
23
0.46104
0.4608
0.05%
0.461046
0.00%
0.461046
0.00%
24
0.45848
0.4608
0.49%
0.460052
0.33%
0.460052
0.34%
25
0.58581
0.589824
0.85%
0.589791
0.84%
0.589791
0.68%
26
0.48563
0.483656
0.42%
0.483775
0.39%
0.483775
0.38%
27
0.59225
0.589824
0.51%
0.589889
0.50%
0.589889
0.40%
28
0.48332
0.483656
0.07%
0.483814
0.10%
0.483814
0.10%
29
0.60493
0.605951
0.22%
0.605226
0.06%
0.605226
0.05%
30
0.32617
0.324893
0.27%
0.324305
0.39%
0.324305
0.57%
31
0.49869
0.481971
3.53%
0.605226
22.49%
0.481551
3.44%
32
0.32617
0.324893
0.27%
0.324305
0.39%
0.324305
0.57%
33
0.46703
0.457838
1.94%
0.546224
16.72%
0.456386
2.28%
8.05286
8.0289
0.30%
8.23635
2.28%
8.02284
0.37%
Standard Deviation
0.88%
6.49%
0.90%
Table 1. Node by Node comparison of transition density.
More experiments have been done for ICS’85 benchmark circuits. Delay of each gate is
approximated with the number of fanouts. For each circuit, average node error, standard deviation
of node errors, and error for total power are measured. Again, node errors are percentage errors
with respect to the average node activity. Results are shown in table 2. For benchmark circuits,
reconvergent fanouts exist in the circuit, therefore probability simulation gives a large error in
most cases even though our new glitch filtering method is applied. For tagged probability
simulation, the improvement of estimation accuracy is significant in some circuits. E.g. c1355,
c6288. These circuits typically have a large component of glitch power. However, for some other
circuits, the application of our new glitch filtering method in TPS does not improve the estimation
accuracy and sometimes even gave a larger error. This is due two factors, first, we found out that
TPS tends to underestimate switching activity for some nodes for those circuits and 2nd, the
original glitch filtering in TPS tends to underestimate the probability to be subtracted. Therefore,
the estimation error for total power is still small. In these cases, a more accurate glitch filtering
will actually increase the error for total power. The application of our new glitch filtering method
gave a relative more “stable” estimation error for different circuits, which is a very important
factor that our new glitch filtering is superior in terms of estimation accuracy comparing to the
original one. In practice, we have no idea which circuit could give a large estimation error; a more
“stable” estimation gave user a lot more confidence about the estimation result.
Circuits ProSim+NEW
TPS
TPS+NEW
Total
Total
Total
Avg. node Std. dev. Power Err. Avg. node Std. dev. Power Err. Avg. node Std. dev. Power Err.
errs. (%)
(%)
(%)
errs. (%)
(%)
(%)
errs. (%) (%)
(%)
c880
11.21
18.23
7.26
8.33
15.34
1.64
8.01
15.65
5.15
c1355
16.78
21.45
18.33
24.21
31.63
32.85
5.82
11.19
5.43
c1908
21.9
33.75
19.66
15
23.11
4.09
17.73
27.85
11.19
c2670
20.63
29.71
15.03
16.56
29.78
7.24
16.65
28.32
9.93
c3540
16.61
36.28
10.08
13.79
26.34
9.78
10.3
25.59
2.42
c5315
20.19
40.05
17.24
11.8
24.39
2.29
13.42
31.52
10.07
c6288
29.63
29.86
26.37
27.39
27.48
32.12
15.65
18.78
4.05
c7552
21.59
39.92
16.39
14.45
27.51
3.17
14.79
31.39
7.78
Table 2 Error comparison of ICS’85 benchmark circuits
The computation speed of TPS+NEW is about 2-3 times faster than that of the logic simulation
over all the vector sequence, while ProSim+NEW is about 20-30 times faster and TPS is about 2
order of magnitude faster than logic simulation. The computation complexity of TPS+NEW is
significantly higher because of the propagation of pairwise dual-transition probabilities. Since
there are only one probability waveform for ProSim+NEW, its computation cost is much lower
than that of TPS+NEW.
6. Conclusions
Most existing gate-level probabilistic approach on power estimation fails to model glitch filtering
effect accurately. However, gate filtering effect has a non-negligible impact on the power
consumption of a circuit. In this paper, we proposed an accurate glitch filtering method based on
the propagation of dual-transition probability (and probability simulation). Our new glitch filtering
method is able to be applied in both probability simulation and tagged probability simulation
techniques. For tree structure circuits where spatial correlations do not exist inside of the circuit,
our new glitch filtering method is able to give very accurate power estimation. For circuits with
reconvergent fanouts, the application of our new glitch filtering method to TPS gives an
estimation that is less erratic than original TPS in terms of estimation accuracy. For some circuits
with a large component of glitch power, up to 28% improvement on estimation accuracy is
obtained by our new glitch filtering method.
Some weakness does exist in our current method. The application of our method to TPS gives
larger error in some cases. Also the computation time is much slower than original TPS because of
the complexity in propagation dual-transition probability. Future work could be the continuous
improvement of the power estimation accuracy and computation time. Since TPS itself tends to
underestimate the switching activity in some cases, a modification of tagged probability waveform
propagation schemes is under investigation. Also, the computation complexity of our method may
be further reduced. Software and algorithm optimization are to be studied.
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