Improved Phase Shedding Techniques in Interleaved
Converters
Anagha Rayachoti
Department of Electrical and Computer Engineering
Missouri University of Science and Technology, Rolla, MO 65409
Abstract—Light load efficiency in interleaved converters is very
poor when compared to single phase converters. Phase shedding
is one of the approaches used to improve this light load efficiency.
This paper analyzes the transient behavior of the system during
phase shedding. The transient voltage response of the system
during the process of phase shedding shows large deviations. A
new method of phase shedding, called the ramp control method is
used to improve this behavior. Later, this new method is
combined with the current sensing control to further improve the
results.
1.
2.
RELATED WORK
In this paper, an interleaved, two phase buck converter
with phase shedding control is modeled using the Simulink
software. The converter is simulated under different phase
shedding control approaches and the resultant voltage and
current profiles are analyzed.
The controls for phase shedding, in general, is obtained
by measuring the total load current of the interleaved
converter. If the load current goes below a certain threshold,
the number of phases which are in operation decreases and
vice versa. But for this paper, we assume that the phase
shedding decision is made at a certain point of time by an
external signal. This is done to simplify the analyses of the
transient behavior.
The converter with ratings, given below, is modeled in
simulink and is as given in Fig.1
VIN = 42 V
VO = 36 V
L = 10 uH
C = 100 uF
IO = 150 A
INTRODUCTION
Multiphase converters or interleaved converters are a parallel
combination of DC-DC converters with an interleaving
difference of 3600/N between the adjacent phases. The main
advantages of the interleaved converters are:
 Smaller inductors are used which makes the
converters more compact.
 Interleaving reduces the ripple current at both input
and the output.
 Efficiency of the interleaved converters is more in
comparison to normal converters.
But one main drawback of these converters is the
decrease in efficiency at light loads. Light loads imply losses
in switches gain prominence, thereby decreasing the efficiency
at light loads. In interleaved converters, these switching losses
cause more problem because of the presence of larger number
of switches. Light load efficiency gains prominence because,
be it in laptops or electric vehicles where this converter finds
its application, the system runs in the light load condition most
of the time.
Phase shedding is one way to improve the light load
efficiency. Phase shedding is the procedure where the number
of active phases is decided based on the load current. Load
current increase causes more phases to become active while
decrease in load current causes these phases to become
inactive and lesser number of phases are in operation.
Major challenge encountered in this process of phase
shedding is the poor transient behavior of the system
immediately after the phase shedding. In this paper, a novel
approach to the process of phase shedding is introduced and
the improvements in the voltage and current profiles of the
system are analyzed.
Fig.1: Two phase buck converter model in simulink
Current mode control technique is used for this converter.
The output voltage is compared to the reference voltage and
the error is passed through a compensator to obtain the
required reference current IREF. The phase currents are
compared with this reference current IREF and the required
switching states are generated. This control model is
illustrated in the Fig.2
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Fig.5: Zoomed in view of the phase currents at 0.02s for a ‘no ramp’ system
Fig.2: Control scheme for one phase of the two phase buck converter in
simulink
2.1 ‘No ramp’ control:
The converter, discussed in the previous section, is
implemented here with the phase shedding control. Phase
shedding decision C2 is taken by external source which
switches OFF phase#2 at 0.02 s and switches it ON again at
0.04 s. Hence the C2 control is essentially a pulse signal. This
control is implemented in the converter in simulink by the use
of a simple multiplier block which multiplies the signal C2 and
the switching state SS2. Thus as C2 becomes OFF i.e. zero, the
SS2 goes into the OFF state, thereby shutting down the phase.
This converter is simulated and the results are as given
below:
Fig.6: Zoomed in view of the output voltage at 0.02s for a ‘no ramp’ system
Fig.7: Zoomed in view of the phase current at 0.04s for a ‘no ramp’ system
Fig.3: Phase currents for a ‘no ramp’ condition
Fig.8: Zoomed in view of the output voltage at 0.04s for a ‘no ramp’ system
For the output voltage simulations, given above in Fig.4,
it is observed that a voltage dip is observed when phase 2 is
switched OFF i.e. a phase shedding decision is made at 0.02 s.
Fig.4: Output voltage for a ‘no ramp’ system
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The falling slope for a 36 V system is given as -36/L while the
rising slope is (VIN - VO)/L i.e. 6/L in our case. Hence we see
that the falling slope is much larger than the rising slope.
Therefore the phase that is shut down goes to zero much more
faster than the rate at which the ON phase can rise to the
required current level. This causes a dip in the total current
which is reflected to the output voltage as well.
The dip is the voltage, as observed from Fig.6, is close to
27 V which is almost a 9 V dip which is unacceptable in any
system. It is also observed from the voltage graph in Fig.8 that
the voltage rise in the system, when the phase 2 is switched
ON again at 0.04 s is about 40 V which is a 4 V rise but this is
not really significant when compared to the dip and hence the
focus, for now, is on eliminating the dip.
One way to resolve this issue would be by decreasing the
falling slope to a suitable value. One way to decrease this
slope would be by not shutting down the phase abruptly and
employing a more gradual shut down in phase.
2.
3.
Y- This control detects the point when the phase 2
current reaches 0. It is 1 if the phase 2 current is non
zero else it is 0.
Z- This control detects the point when the phase 2
current reaches the average value. It is 1 when the
current is equal to the average value else it is 0.
2.2 Ramp control
2.2.1
‘No current sensing’ control
Fig.9: State flow chart for the ramp control in simulink
To improve the behavior of transient voltages in the
above system, the phase to be shut is gradually brought into an
OFF state. This is done by making the IREF curve of the second
phase follow a falling ramp when it is shut down. Basic
solution can be summed up as given below:
 Phase 2 follows IREF under steady state conditions.
 Phase 2 is shut down implies it follows IREF –IRAMP
until its current becomes 0.
 Phase 2 is OFF implies it follows 0 current.
 Phase 2 is switched ON implies it follows IRAMP till
its current reaches the required value.
 Phase 2 is ON implies it follows IREF as in steady
state conditions.
Fig.9, shown above, is a state flow chat created in
simulink and it describes the different states and the transition
between the states. During the steady state operation, the
system is in the state 10 (IREF is 1 and IRAMP is 0). Once the
phase shuts down, then irrespective of the value of Y and Z,
the state changes to 11 (IRAMP is negative here). Once Y
becomes 0, the state changes to 00. Once again as the phase
becomes ON, irrespective of the value of Y and Z, the system
is in the state 01. And once Z becomes 1, the state of the
system changes to 10.
With the controls C2, Y and Z defined, the state diagram
is converted into a flip flop design and integrated into the
simulation. The clock pulse used for this flip flop
implementation has a frequency of 1000 KHz. The flip flop
implementation is as given below in Fig.10.
Implementing this control for the converter is very
complicated. Definite controls for detecting the point where
current crosses 0 and the point where current reaches the
average value need to be defined. Doing so may prove to be
cumbersome in analog domain or rather the simulink domain.
Hence state machine diagrams are used for implementing this
control.
For the state machine diagram, we need to first define the
states and the controls required for the states. Here, two statesone for the reference current IREF and another for the ramp
current IRAMP are defined. There are four possible
combinations of these two states- IREF IRAMP (Q2Q1)00,01,10,11. At any given point of time, a system is in one of
these four states. The state of the system is decided by certain
controls. In this case, the controls are:
1. C2- This control shows if the phase 2 is in ON or
OFF mode. This control has already been described
in the previous section. Its value is 1 when the phase
is ON and 0 otherwise.
Fig.10: Flip flop implementation of the ramp control
The value of IRAMP needs to be chosen such that the rising
slope of phase 1 is equal to the falling slope of phase 2. The
rising slope of phase 1 is approximately equal to 6 x 10 5 i.e.
(VIN - VO)/L and hence a value of 6 x 105 or less for IRAMP will
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solve the problem of voltage dips. Hence, in this simulation,
the value of IRAMP is taken as 6 x 105.
The value of IRAMP is positive when the phase is ON and
is negative when the phase is OFF. For C2=0, IRAMP has a
negative sign and for C2=1, IRAMP has a positive sign. This is
implemented as shown in the figure given below:
This converter is simulated and the results are as given
below:
Fig 14: Zoomed in view of output voltage at 0.02s for ramp control with a
ramp of 6×105
The voltage dip is observed to be about 6 V, which is
definitely better than the no ramp condition but it is seen that
there still is a scope for improvement.
Reducing the falling ramp by ten times will give us better
results which are as given below. But it is observed that there
is a wide dip of 1 V in the system.
Fig.11: Phase currents for ramp control with a ramp of 6×10 5
Fig.15: Phase currents for ramp control with a ramp of 6×104
Fig.12: Output voltage for ramp control with a ramp of 6×10
5
Fig.16: Output voltage for ramp control with a ramp of 6×104
Fig.13: Zoomed in view of phase currents at 0.02s for ramp control with a
ramp of 6×105
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Fig.20: Phase currents for a ramp of 6×104 with current sensing control
Fig.17: Zoomed in view of phase currents at 0.02s for ramp control with a
ramp of 6×104
Fig.21: Output voltage for a ramp of 6×104 with current sensing control
Fig.18: Zoomed in view of output voltage at 0.02s for ramp control with a
ramp of 6×104
2.2.2
‘Current sensing’ control
The wide dips during the transient phase can be decreased
by programming the controller such that the total current
passing through the load remains constant at all times i.e. if
the controller senses that IO is decreasing, it should increase
the duty cycle should increase thereby preventing the dip in
VO. So now both VO and IO are sampled and compared with a
certain reference. This type of control is also known as the
current sensing control technique which is illustrated in
Fig.19.
Fig.22: Zoomed in view of the phase current at 0.02s for a ramp of 6×104 with
current sensing control
Fig.19: Current sensing control technique
The converter is simulated with the current sensing
control technique and the results are as given below:
Fig.23: Zoomed in view of the output voltage at 0.02s for a ramp of 6×104
with current sensing control
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For a ramp of 6×104, it is seen that the wide voltage dip is
only about 0.2 V which is a very huge improvement compared
to the previous case.
Droop control improves the voltage profile of the system,
thereby eliminating the transient disturbances in the system.
The only disadvantage with this control is that current needs to
be measured to implement this control and current sensing is
sometimes a challenge in itself.
3.
CONCLUSION
In this paper, phase shedding in interleaved converters has
been introduced and the challenges in the transient behavior
have been analyzed through the simulation results. Through
the ‘ramp control’ approach introduced in this paper, it is seen
that the transient behavior of the output voltage of the system
improves. It is also seen that the ‘ramp control’ approach
when combined with the ‘current sensing’ control further
improves the voltage profile. Hence this approach can be used
for increasing the light load efficiency of the system without
disturbing the system behavior during transients.
4.
ACKNOWLEDGEMENT
This research is currently sponsored by the Intelligent
Systems Center(Missouri University of Science and
Technology)
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