Majority Logic Decoder for Fault Detection and Correction in
Memory Applications
A.Sneha, M. Tech, Department of ECE,SNIST ,Hyderabad.
sneha.adelli@gmail.com
Abstract: Memories are the important components in
most the digital systems to store and retrieve the data.
The faults in memories include single event upset
(SEU), soft errors, multiple cell upset (MCU) etc, flip
or reverse the stored data on memory cell. An
efficient and an effective code are required to detect
the errors and to correct them for protection of
memories from the faults. New MLDD has been
implemented using Euclidean Geometry low density
parity check (EG-LDPC) codes with extra logic is
used in addition to stop immediately in one cycle
when there is no error in the read data instead of
decoding for whole code word size. Fault secure
encoder and decoder is also desgned.
1.
Introduction
Errors occur in memories change a data value or
an instruction. Memories have been suffering from
hard and soft errors. Hard errors are referred as
permanent damages to the memory. The solution is
only replacing the entire memory chip. Soft errors
will not affect the memory hardware, but cause the
memory cell to change its state to a different value
and errors in the processing data. Single Event Upset
(SEU) is a type of phenomenon in which state of the
memory changes by ions or electro-magnetic
radiation. When a high energetic particle strikes the
memory cell, it discharges the charge in to the
memory cell [1][2]. These single event effects are
soft errors appear in memory chips, microprocessors
and power transistors etc. SEU is not considered as a
permanent damage in digital devices.
To recover the memories from failures, some
techniques are required. Some commonly used error
correction and detection methods are Triple Modular
Redundancy (TMR) and Error correcting codes
(ECC).
TMR system consists of three systems which perform
a process and the majority of the process result is
selected and provides output by a majority voting
system. This is a fault tolerant system which has
large area and complexity overhead [3]. Hence,
powerful ECC with check bits are considered as the
best codes [4] to reduce the soft errors.
2. LDPC CODES
Low density parity check codes are a special class
of linear block codes. These codes have less number
of 1’s in comparison to number of 0’s, hence name
comes. These codes can be represented in matrix
form and as well as in graphical form.
EG-LDPC codes are a type of LDPC with simple
encoder design [16][]17][20][21]. Its information bit
length for encoding and length of encoded data etc
are given by
Information bits k - 22S - 3S ,
Length of encoded data - 22S - 1 Dimensions of
parity check matrix - n x n, Minimum distance (d)
- 2S + 1.
In general, error detection and correction
capability of codes is decided by hamming distance.
( Dmin - 1 ) - Number of errors detection,
( Dmin – 1 ) / 2 – Number of errors correction.
Rows of a generator matrix are the basis of linear
codes. Codeword using these codes are in the form of
C=IxG
I- Identity matrix, G- Generator
matrix = [ I | X ], X- parity bit matrix ‘(n-k)xk’
Parity check matrix ‘H’ and is in the form of H = [ PT | In-k ]
Here P- parity bit matrix with ‘ kx(n-k)’.
3. MEJORITY LOGIC DECODER
A new design of memory with encoder and
decoder is shown in Fig.1 [25][27][28]. Encoding of
data is to be done and placed in memory. Data is read
from memory by decoder circuit to check the errors
with the help of majority decoder circuit. Detection
of errors in the data read is depends on the hamming
distance between code words. EG-LDPC codes are
used for encoding the information bits. Encoding of 7
information bits using EG-LDPC codes is shown in
Fig.2. It requires 8 parity check bits. Then the
encoded data is stored in the memory. Because of
soft errors if, any bits are flipped in the stored
encoded data of memory, the decoded data may be
different from the original data. Here majority logic
decoder is designed in such a way that it can detect
and correct the errors in the read encoded data
automatically.
Figure 1: Memory
Encoder and with MLD.
with
result of corrected circuit will be placed in the
starting bit place as shown in Fig.3
Figure 3: Majority Logic Decoder with
automatic Correction circuit.
4 PROPOSED DESIGN
This design works well with an assumption that
encoder and decoder circuits which are external to
the memory. But this assumption is not valid in all
times. Encoder and decoder circuits may also have
faults and can produce a wrong encoded and decoded
data [29]. New design is proposed to find the faults in
encoder and decoder circuits based on the codeword
generation[30][31]. If it is found that there are errors
in codeword, the encoding and decoding process has
to be repeated. This new design is as shown in Fig.4.
EG-LDPC
Figure 4: Error detection circuit for both Encoder
and Decoders.
Figure 2: EG-LDPC Encoder circuit with
7 information bits and 8 parity bits.
The majority logic decoder with detector is shown
in Fig 3. The read data of 15 bits are stored in right
shift register. This shift register is of parallel in and
serial out register. The data stored in the shift register
is then given to a XOR matrix. XOR matrix is a
combination of different bits with the last bit in
register. The result of XOR matrix will be given to a
majority logic which gives output of one bit depends
on number of 1’s and 0’s. The result of majority logic
will be XORED with last bit in the shift register
which acts as a corrector circuit. Then the shift
register data is shifted one place to the right and the
In order to reduce the number of clock cycles
required to decode and correct the errors, extra circuit
is designed. This circuit is used in combination with
plain MLD. The code word read from the memory
is to be multiplied with transposed parity check
matrix. If the result is zero indicates the code word is
correct otherwise the codeword is incorrect. It takes
one clock cycle incase of no error in codeword. If
there are any errors, the code word undergoes the
shown process to make error free. Syndrome check to
detect error is as shown in below Fig 5.
Figure 5: Error detector for (15,7,5) EG-LDPC.
Experimental Results:
The design is coded in verilog description language.
The simulation results of the proposed majority logic
design are done by using XILINX ISE tool. The
experimental result of encoder and decoder are
shown in figure 6 and 7. Result of 7-bits of data with
an example is shown here. The code can correct 2 bit
errors in information bits and as well as in parity bits.
Here the example is taken, error free, one bit error
and with 2 bit errors. The seven bits of the codeword
after error correction is the output. The final result is
as shown in figure below.
Acknowledgements
The authors would like to thank the Management
and Principal of Sree Nidhi Institute of Science and
Technology, Hyderabad for valuable support,
providing excellent facilities and encouragement.
References
[1]
Gaurav Saxena, Rekha Agrawal, Sandhya
Sharma “Single Event Upset (SEU) in
SRAM”, International
Journal of
Engineering Research and Applications,
Vol. 3, Issue 4, pp. 2171-2175, Aug 2013.
[2]
Robert C. Baumann “Radiation-Induced Soft
Errors
in
Advanced
Semiconductor
Technologies”, IEEE Transactions on
Device And Materials Reliability, Vol. 5,
No. 3, pp. 305-316, Sept 2005.
[3]
J. Von Neumann, “Probabilistic logics and
synthesis of reliable organisms from
unreliable components”, pp. 43–98, 1956.
Charles W. Slayman “Cache and Memory
Error Detection, Correction and Reduction
Techniques for
Terrestrial Servers and
Workstations”, IEEE Transactions On
Device And Materials Reliability, Vol. 5,
No. 3, pp-397-404, Sept2005.
[4]
Figure 6: Encoder circuit output.
[5]
Elaine Ou and Woodward Yang “Fast ErrorCorrecting Circuits for Fault-Tolerant
Memory”, IEEE, International Workshop on
Memory Technology, Design and Testing,
2004.
[6]
Priyanka P. Ankolekar, Roger Isaac, and
Jonathan W. Bredow Multibit “ErrorCorrection
Methods
for
LatencyConstrained Flash Memory systems”, IEEE
Transactions On Device And Materials
Reliability, Vol. 10, NO. 1, pp. 33-39, Mar
2010.
[7]
Riaz Naseer and Jeff Draper ” ” DEC ECC
Design to Improve Memory Reliability in
sub 100nm Technologies” , IEEE ICECS,
pp.586-589, 2008.
[8]
S.Baskar, M.Saravanan “Error detection and
correction Enhanced decoding of difference
Set codes for memory application”
International Journal of Advanced Research
in
Computer
and
Communication
Engineering, vol-1, Issue 10, pp. 816-820,
Dec 2012.
Figure 7: Decoder circuit output.
5. CONCLUSION
The proposed design takes one clock cycle if the
codeword is error free. If there are errors in codeword
the process need to be repeated for 15 clock cycles.
Fault secure encoder and decoder are designed.
Errors in memory, encoder and decoder circuits can
be corrected with this design.
[9]
[10]
Michael A. Bajura, Younes Boulghassoul, Riaz
Naseer, Sandeepan DasGupta, Arthur F.
Witulski, Jeff Sondeen, Scott D. Stansberry,
Scott D. Stansberry, Jeffrey Draper, Lloyd
W. Massengill and John N. Damoulakis”
Models and Algorithmic Limits for an ECCBased Approach to Hardening Sub-100-nm
SRAMS”, IEEE transactions on nuclear
science, vol. 54, no. 4, pp. 935-945, Aug
2007.
Peterson, W.W. and Brown, D.T. “Cyclic
Codes for Error Detection” IEEE
Proceedings
of the IRE ,Vol-49 , pp. 228
– 235, Jan 1961.
Nano-scale Memory”, SRI Comput. Sci.
Lab. Tech. Rep. CSL-0703, pp. 1-22, 2007.
[18]
Xiao Li Yi, Zhu Ming, Zhang Yan Jing, Luo
Hong Wei “Design EG-LDPC Codes for
Soft Error Mitigation in Memory”, IEEE,
pp. 328-332, 2011.
[19]
T. Kuroda, M. Takada, T. Isobe and 0.
Yamada “Transmission Scheme of Highcapacity FM Multiplex Broadcasting
System”,
IEEE
Transactions
On
Broadcasting, Vol. 42, No. 3, pp. 245-250,
Sept 1996.
[20]
Pedro Reviriego, Juan A. Maestro, and Mark
F. Flanagan “Error Detection in Majority
Logic Decoding of Euclidean Geometry
Low Density Parity Check (EG-LDPC)
Codes”, IEEE transactions on very large
scale integration (VLSI) systems, Vol. 21,
No. 1, pp. 156-159, Jan 2013.
[11] Alexios Balatsoukas-Stimming and Apostolos
Dollas
“Fpga-based
design
and
implementation of a multi-gbps ldpc
decoder” Field Programmable Logic and
Applications (FPL), 2012 22nd International
Conference, pp. 262 – 269, Aug. 2012.
[12] Sarah J. Johnson, Steven R. Weller “ A Family
of Irregular LDPC codes with Low
Encoding
Complexity”,
IEEE
Communications Letters, Vol- 7, No. 2, pp.
79-81, Feb 2003.
[13]
[14]
Thomas J. Richardson, M. Amin Shokrollahi
and Rüdiger L. Urbanke “ Design of
Capacity Approach Irregular Low Density
Parity Check codes”, IEEE Transactions on
Information Theory, Vol- 47, No. 2, pp.
619-637, Feb 2001.
Yu Kou, Shu Lin and Marc P. C. Fossorier
“Low-Density Parity-Check Codes Based
on Finite Geometries: A Rediscovery and
New Results”, IEEE Transactions on
Information theory, Vol. 47, No. 7, pp.
2711-2736, Nov 2001.
[15] Ravi palanki, Marc Fossorier, Jonathan Yedidia
“Iterative Decoding of Multi step Majority
Logic Decodable codes”, IEEE Transactions
on Communications, June 2007.
[16] Lavanya Thunuguntla, Bindu Madhavi K, and
Ramesh Kumar Reddy C “Secure
Transmission for Nano memory using EGLDPC”, IJERA, Vol. 2, Issue 2, pp.292-299,
Mar 2012.
[17]
S. Ghosh and P. D. Lincoln “Low-Density
Parity Check Codes for Error Correction in
[21] Teena Ann Thomas and Ashad Kumar A “High
Performance Error Detection and Correction
Technique for Memories Using Difference Set Codes”, Int. Journal of Engineering
Research and Applications, Vol-3, Issue-5,
pp.1045-1050, Sep 2013.
[22]
D.Subalakshmi and Major. P.S.Raghavendran
“Error Identification and Correction for
Memory Application using Majority Logic
Decoder and Detector”, International
Journal of Computer Applications Vol 64,
No.10, pp. 8-13, Feb 2013.
[23]
Bane Vasic and Shashi Kiran Chilappagari
“An Information Theoretical Framework For
Analysis and Design Of Nanoscale FaultTolerant Memories Based On Low-Density
Parity-Check Codes”, IEEE Transactions On
Circuits And Systems I: Regular Papers,
Vol. 54, No. 11, pg no. 2438-2446, Nov
2007.
[24]
Shu Lin and George Markow sky “On a class
of one step majority logic decodable cyclic
codes”, IBM Journal of research and
development, vol.24, No.1, Jan 1980.
[25]
Radhakrishnan, R, Sankaranarayanan, S and
Vasic, B “Analytical Performance of OneStep Majority Logic Decoding of Regular
LDPC Codes”, Information Theory, 2007.
ISIT 2007. IEEE International Symposium ,
2007.
[26]
[27]
Dhanasekaran S.G and Mahendra Babu G.R “
High Performance Error Detection and
Correction for Memory Applications using
Majority Logic Decoder or Detector”,
International
Journal
of
Advanced
Information Science and Technology, Vol12, No-12, pp. 8-15 , Apr 2013.
Shih-Fu Liu, Pedro Reviriego and Juan
Antonio Maestro “Efficient Majority Logic
Fault Detection With Difference-Set Codes
for
Memory
Applications”,
IEEE
Transactions on Very Large Scale
Integration (VLSI) systems, Vol. 20, No. 1,
pp. 148-156, Jan 2012.
[28] G.Boopathi Raja and M.Madheswaran “Logic
Fault Detection and Correction in SRAM based
Memory Applications”, International conference on
Communication and Signal Processing, pp. 215-220,
Apr 2013.
[29]
Helia Naeimi and Andr´e DeHon. “Fault
Secure Encoder and Decoder for Memory
Applications”, 22nd IEEE International
Symposium on Defect and Fault Tolerance
in VLSI Systems, pp. 409-417, 2007.
[30]
Dr.M.Chandrasekar and P.Dhinakar “VLSI
Techniques for Fault secure Encoder and
Decoder in Nano Memory Applications”
International Conference on Optical Imaging
Sensor and Security, 2013.
[32] Helia Naeimi and Andre’ DeHon “Fault secure
encoder and decoder for nano memory
applications”, IEEE transactions on very
large scale integration(VLSI) systems,Vol17, No.4, pp. 409-417, Apr 2009.