Circuits, Devices, Networks and Microelectronics
ECE 3434
Problems in non-ideal Opamps
Version 2.3
Defaults: All resistances are in kW and currents in mA, unless otherwise indicated.
15-30. Assume non-ideal ideal opamps with zero frequency gain 52dB and unity-gain frequency fT =
2MHz. Determine  (=feedback factor), f3dB , and transfer gain vO/vS for each of the configurations
Answers: (A) 0.2, 4.94 V/V, 400kHz, (B) 0.2, -3.95 V/V 400kHz, (C) 0.125, -5.88 V/V, 250kHz
15-31. A compensated opamp with unity-gain frequency fT =
2.5MHz and zero-frequency gain 66dB is connected in an
inverting configuration as indicated. Determine:
(a) R2 needed for f3dB bandwidth 200 kHz and the (inverting)
gain that results.
(b) Bandwidth and (inverting) gain if R2 =150 k
15-32. Assessment of the open-loop gain of a compensated opamp intended for high-frequency
operations indicate that the gain = 48dB at 20 kHz and 66dB at 0.2 kHz. Determine its 3-dB frequency,
unity-gain frequency (= fT) , and zero-frequency gain (= AV0). (Hint: Sketch the Bode magnitude plot for
the opamp and overlay it over the points identified.
Circuits, Devices, Networks and Microelectronics
15-33. (a) Show that by cascading two identical (non-inverting opamp amplifier) stages, each with lowpass frequency 3dB corner f1 results in an amplifier with overall 3dB (  A / 2 ) corner
f 3dB 
2  1 f1
(b) Design a non-inverting amplifier with DC (zero-frequency) gain = 36 dB using a single highperformance integrated–circuit CMOS opamp having fT = 32 MHz and zero frequency gain = 80dB.
What f3dB results?
(c) Now redesign the amplifier of (b) cascading two identical amplifiers, each with a DC (zerofrequency) gain of 18 dB. What is the overall 3dB frequency obtained?
(d) Now redesign the amplifier of part (b), to be three stages, each with a zero-frequency gain =
12dB. What f3dB results? (Note that the formula under part (a) has to be revised (for which you will find
that f3dB = 0.51f1.)
(e) Redesign the amplifier of part (b), to be six stages, each with a zero-frequency gain = 6dB.
What f3dB results?
This exercise illustrates the effect of cascading closed-loop opamps to achieve an overall bandwidth
greater than that which can be achieved by means of a single opamp.
Answers: (b) 500 kHz, (c) 2.57MHz (d) 4.08 MHz
15-34. (a) For a high performance CMOS opamp with SR = 3 V/s, what is the highest frequency at
which an undistorted 12V peak-peak sine wave can be produced at the output?
(b) What is the maximum undistorted (peak-peak) amplitude if the frequency is 2MHz?
(c) What is the highest frequency for which the peak-peak amplitude is 5.0V?
(Answers: 0.25 MHz, 1.5V, 0.3 MHz)
15-35. In designing circuits with opamps there are two
frequency (or speed) limitations: (1) finite gain-bandwidth,
as represented by fT, and (2) finite output slew rate SR.
Consider the circuit shown. Assume that fT = 4MHz, SR =
0.5 V/s, and Vout(max) = 10V (determined by the power
supply). vS is a sinusoidal signal with input amplitude VS.
(a) If vS = 0.25V what is the maximum undistorted
output frequency?
(b) If f = 50kHz, what is the maximum value of vS for an
undistorted output signal?
(c) If vS = 100mV what is the useful frequency range of
(d) If f = 5kHz, what is the useful range of input
amplitude vS?
Circuits, Devices, Networks and Microelectronics
Circuits, Devices, Networks and Microelectronics
15-36. An opamp is employed to strengthen weak amplitude
0.5us pulses to output amplitude 4.0V. The slew rate of the
opamp causes a finite rise/fall time pulse distortion as shown.
(a) Assuming that the next stage is triggered by these pulses at
the 2.5V level, what delay is induced if the SR = 10V/s?
(b) If it is required that no more than a 0.1s delay be induced
by the pulse amplifier, what opamp SR is required?
15-37. A non-ideal BJT opamp for which the zero
frequency gain = 54dB and fT = 4 MHz has finite input
resistance Rid = 200 k. If it is configured as a noninverting amplifier as shown, determine
(a) Equivalent component values, Req and Ceq of the
input impedance
(b) At what frequency does Ceq begin to shunt Req?
(c) What is the approximate input |Zin| at f = 20kHz?
15-38. A high-performance CMOS opamp with zerofrequency gain 72dB and gain-bandwidth product 100 MHz
has finite output resistance RO = 20k. If configured as an
inverting amplifier as shown, determine
(a) Component values Req and Leq of the output impedance
(b) |Zout| at f = 100 kHz.
Answers: 50 320H, (b) 500 
15-39. An opamp is used in an inverting configuration for which R2 = 200 k and R1 = 1 k, with the
input grounded. The DC output voltage = -0.5V. What is the input offset voltage, VOS, assuming that the
input bias current is negligible?
15-40. For the differential amplifier shown, the
opamp has VOS = 3 mV, IB = 0.2 mA, and IOS = 50 nA.
What is the worst-case DC offset voltage at the output?
Circuits, Devices, Networks and Microelectronics
15-42: In many cases the CMRR is due to more asymmetries
in the circuit topology rather than to the finite CMRR
limitations of the opamp. As a case in point, consider the basic
single-opamp diff-amp construct shown and assume that R2/R1
=  and R4/R3 =  + , where  << . The output can then be
derived as a diff-amp with differential gain A1 and commonmode gain A2, i.e.
v 0  A1 (v1  v 2 )  A2 (v1  v 2 ) 2
(a) Determine A1 and A2 and find the ‘topology–induced’
CMRR = |A1/A2| in terms of  and .
(b) Find the topology-induced CMRR when R1 = 10 k, R2 =
400 k, R3 = 10k, and R4 = 410 k.