APPROACHES AND CHALLENGES FOR 3D IC PACKAGING
Charles G. Woychik, Sangil Lee, Guilian Gao, Liang Wang, Hong Shen, Akash Agrawal, Mohamed
Elassar, Scott McGrath and Sitaram Arkalgud
Invensas Corporation
3025 Orchard Parkway
San Jose, CA USA
Cwoychik@Invensas.com
ABSTRACT
Recent product announcements highlight the emergence of
higher volume TSV-based products in the marketplace.
Major industrial players have launched products leveraging
TSV technology such as the DDR4 3D stacked DIMM, high
bandwidth memory (HBM), and high performance graphic
processors using a 2.5D Si-interposer. While offering
considerable performance, power and density advantages,
packaging costs still remain high and need to be reduced
further. This paper presents a detailed study and data on
assembling a 2.5D test vehicle. The test vehicle used
consisted of two 10mm x 12 mm micro-bumped die having
solder capped Cu-pillars with a 60um pitch attached to a
19mm x 27mm Si-interposer with a thickness of 100um and
TSVs having a dimension of 10um x 100um. This Siassembly was then attached to a standard buildup substrate.
A discussion of the challenges for thermal compression
bonding thin die to an interposer and the impact of
subsequent flip chip attach reflow of the Si-assembly to the
interposer on the integrity of the micro-bumped die
interconnects is discussed. Once the optimized bonding
conditions were achieved, samples were built and subjected
to MSL L3 preconditioning and thermal shock testing
(TST). The assembly challenges and the resulting reliability
tests results will be discussed in this paper.
Key words: 2.5D, 3D IC, TSV, Micro-bumped die, Siinterposer, CTE, warpage, JEDEC reliability specifications,
chip stacking.
INTRODUCTION
Very high end 3D packaging uses through silicon vias
(TSVs) to produce a three dimensional stacked
semiconductor chip structure. The ability to create a three
dimensional heterogeneous integrated semiconductor
structure offers numerous benefits, such as power reduction,
performance improvement and miniaturization. The
viability of the semiconductor technology to create these
TSVs in volume has been demonstrated. However, making
this a cost effective technology is where the focus needs to
be in order to make this viable for high volume
manufacturing [1-3].
The recently announced 2.5D AMD Radeon R9 Fury
module shows the integration of a 3D memory stack along
with a large die GPU on a Si-interposer as shown in Figure
1. Prior to this announcement the Xilinx Virtex 7 2.5D Siinterposer product was the one most often cited at
conferences and in publications. The Virtex 7 has four
planar rectangular die attached to a Si-interposer and has a
very high ASP. In comparison, the AMD product is a more
sophisticated design since it uses 4 HBM 3D memory stack
modules with TSVs along with a large die GPU, all of
which are attached to a Si-interposer. It was also
dramatically cheaper than the Xilinx offering. The cost of
making TSVs and 3D stacking is coming down
dramatically.
To enable wide adoption of 2.5D and 3D technology, an
important question must be answered: Who will do the 3D
IC assembly? In the past, the semiconductor fabricator
(IDM) designed and manufactured the die and then handed
it over to the packaging facility for assembly and test. As
flip chip technology evolved, a new sector called the
“middle end” developed which included RDL, wafer
bumping and test. This middle region has further evolved to
include micro-bumping, wafer thinning and backside reveal,
interposer fabrication, wafer level assembly and 3D wafer
level test. As the industry develops this technology, we
realize that the packaging solution for the foundry is likely
to be different from that of the OSAT. The turnkey chip-onwafer-on substrate assembly flow suits a foundry model
very well but does not involve an OSAT. Alternative
assembly flows that use chip-to-interposer-to-substrate
approach are much more OSAT inclusive.
In this paper we focus on an OSAT type of assembly
method that can offer a high yielding, and therefore lower
cost, 3D packaging solution.
(a)
Figure 1. Photo of AMD’s large die GPU and 4 Hynix
HBM modules attached to a Si-interposer (Image courtesy
of AMD).
In developing a package solution, one must engineer this
package to be able to pass the JEDEC standard module and
board level reliability tests, which are temperature cycling,
high temperature storage, temperature and humidity testing,
unbiased high accelerated stress testing (HAST), and
pressure cooker testing. Based on our experience in
developing reliable packages, we know that understanding
stress and its impact through the assembly process can have
a dramatic effect on the final warpage of the assembled
package. This warpage will affect the final reliability of the
package, which is why it is paramount to properly engineer
the package & assembly process in order to minimize the
ITP and substrate warpage. Much research has been done to
investigate the effect of warpage on reliability of organic
flip chip packages and substrates, and this knowledge can be
applied to current 3D IC packaging designs [4-7].
(b)
Figure 2. A schematic illustration of the 2.5D test vehicle
having two micro-bumped die attached to a Si-interposer,
which is then attached to a buildup substrate. (a) overall test
vehicle; (b) partial X-sectional corner view showing the part
with underfill and mold cap.
TEST VEHICLE DESIGN
The 2.5D test vehicle used in this study is schematically
illustrated in Figure 2. Two micro-bumped die (MBD) are
attached to a Si-interposer (ITP), which is then attached to a
standard buildup substrate. Details of the test vehicle design
are given in Table 1. In this test vehicle, the ITP dimensions
are 19.25mm x 27.05mm x0.1mm. The buildup substrate
has a 3-4-3 layer structure. On the top surface of the ITP are
two MBD with dimensions of 10mm x 12mm and a
thickness of 0.2mm. The two MBDs were spaced 2mm
apart.
Table 1. The Invensas 2.5D test vehicle specification
FABRICATION OF Si-INTERPOSER (ITP) AND
MICRO-BUMPED DIE (MBD)
The ITP was made on 300mm wafers using a via-mid
process. The TSVs had a 10um diameter and were 100um
deep. A standard DRIE dry etch process was used to form
via holes in the wafer. A standard PECVD TEOS process
was used to deposit the SiO2 isolation layer. A Ta-Cu
barrier/seed layer was deposited and the vias were filled
using a Cu-electroplating process. There was one RDL layer
on the front side and one layer on the backside. Front side
passivation was silicon oxide. The backside passivation was
a combination of low temperature silicon oxide and low
temperature cured polyimide. Figure 3 shows a SEM crosssection image of the interposer with pads for microbump
attachment on the top and UBM for flip chip ball on the
bottom.
(a)
(b)
Figure 4. (a) An SEM image of the reflowed, solder capped
microbumps on a MBD; (b) SEM image of a pillar with Cu
base and solder cap.
Figure 3. SEM image of a cross-section of the Si-interposer
used for this study.
The MBD was also made on a 300mm wafer. The surface
was passivated with silicon oxide. One copper RDL layer
was used for daisy chain connection between the
microbumps. The 35um diameter Cu pillars with SnAg
solder cap were produced by electroplating. The solder cap
was reflowed to form the half-dome shape after the plating
resist was stripped. Figure 4 shows SEM images of the
solder capped Cu-pillar bumps on the MBD.
ASSEMBLY PROCESS FLOW
Different assembly flows including fab centric and OSAT
centric flows were evaluated at Invensas. In this paper, we
concentrate on the OSAT friendly, substrate-last assembly
flow shown in Figure 5.
For this assembly flow, a singulated ITP, either with or
without backside solder bumps was held in place with a
vacuum fixture. This study used an ITP having ENIG pads
on the topside for MBD attach, as shown in Figure 4. The
two MBD were then attached to the ITP with in-situ solder
reflow using a thermal compression bonder and then
underfilled. The assembled ITP was attached to the substrate
using a conventional mass solder reflow process. In this
study the solder balls were placed on the substrate, and then
the substrate was attached to the ITP using mass reflow. As
shown by Gao, et. al[8], this assembly flow minimizes the
ITP warpage with vacuum during the MBD attachment.
Consequently it can meet the very narrow assembly window
of 11um for the MBD attachment. More details on these
process flows are outlined in a recent publication [9]. The
focus of this paper will be the process assembly
development related to process conditions and materials
selection.
Figure 6. X-ray image showing microbump solder bridging
in the perimeter array after assembly to the ITP.
Figure 5. Substrate-last process flow using a solder bumped
interposer with a non-solder bumped substrate (left side)
and a non-solder bumped interposer in combination with a
solder bumped substrate (right side).
Solder capped copper pillar micro bumps were used to
attach the MBD to the ITP. The perimeter array is 60um
pitch and the inner array is 120um pitch. The ITP was
attached to the 3-4-3 buildup substrate with 110um diameter
solder balls. The perimeter array was 180um perimeter pitch
and the inner array was 250um pitch. Solder balls were
attached to the substrate prior to die assembly. Both the
MBD and the ITP are underfilled using commercially
available capillary underfill materials. There are two units
on each substrate strip. Following underfill cure, the entire
strip is molded with a transfer mold process using a
Invensas qualified HVM mold material.
ASSEMBLY PROCESS DEVELOPMENT
In this work, design of experiments (DOEs) were used to
achieve a high yielding MBD to the Si-ITP attachment
process. When the initial set of parts were built, the primary
failure mode was microbump solder bridging. Figure 6
shows an X-ray image of these bridges in the 60um pitch
periphery array of the microbumps after assembly to the
ITP.
To achieve the final process window, three different DOEs,
two for the MBD to ITP attachment process by TCB, and
one for flux selection, were designed and carried out. The
first DOE focused on optimization of thermal and
mechanical process parameters affecting solder bridging of
the microbumps. The second DOE validated the stability of
the assembly process. The third DOE studied the effect of
two different fluxes on microbump joint integrity
DOE1: TCB PROCESS OPTIMIZATION
The primary objective of DOE1 was to decouple thermal
and mechanical process parameters in MBD attach using a
TCB bonder. Thermal process parameters included bond
stage temperature, bond head peak temperature, time at peak
temperature and vacuum release temperature during cool
down. During bonding one must account for the collapse of
the solder capped Cu-pillar due to the melting of the solder.
In order to prevent total collapse, the TCB bonder used in
this study has a z-displacement setting to control the amount
of z-displacement of the head. This amount of controlled zdisplacement after solder reflow is called the “Melt Setting.”
Task 1 used a fixed melt setting to identify a stable thermal
process window. Then Task 2 optimized the mechanical
parameters, i.e, the melt setting, within the optimized
thermal process conditions.
Task 1- Thermal Process Parameters Evaluation: In this
task, the three variables were evaluated: bond stage
temperature, time at peak temperature of the bonding head,
and vacuum release temperature during cool down. The
peak temperature of the bonding head was set at 305C. The
melt setting use was 6um. This experiments produced the
nominal MBD interconnect height of 43.2 um. The target
height that we wanted to achieve was 35um, which was
based on assembly window analysis [8]. Figure 7 shows a
SEM of the resulting solder interconnect from this build.
Under these conditions, the failure mode has shifted from
solder bridging to solder opens. For all four legs of the
DOE there were solder opens as shown in Table 2, which
implies that the thermal process window is stable enough
not to result in short failures and mechanical process
window is independent of thermal process parameters
because no short failures were observed at even higher
temperature and longer peak.
Solder
wetting
6um
8um
10um
Figure 7. The nominal MBD solder interconnect height of
43.2um from DOE1 Task1.
--- Melting Setting
Figure 8. DOE1 Task 2-TCB profile
Parts built using these process parameters were crosssectioned for stand-off height evaluations. The result shows
a slight bow of the die with the stand-off height in the center
approximately 2um taller. We believe that this bow was due
to a temperature gradient across the MBD that causes an
uneven gap height. Figure 9 shows the edge MBD solder
joints having a height of 40um and the center die solder
joints having a height of 42um.
Table 2. DOE1 Task1–Thermal process parameters and
results
Task2: Mechanical Process Parameters and TCB Process
Design: In Task 2, we selected upper limits of the thermal
process window identified in Task 1, which do not induce
short failures, to guarantee stable solder interconnection.
The mechanical process condition, i.e, the melt setting was
then adjusted to eliminate solder opens. As shown in Table
3, melt settings of 6um, 8um and 10um were evaluated.
40um
~40um
m
Edge
42um
~42um
Center
Figure 9. Comparison of edge and center MBD interconnect
height using DOE1 bonding conditions.
Table 3. Melt settings with thermal process conditions used
in DOE1 Task 2
From this work the electrical testing of the daisy chain test
structure confirmed no solder opens and no shorts when
using a melt setting of 10um. Electrical testing and X-ray
was also used to verify no short failures. The thermal
bonder conditions used for this build are shown in Figure 8,
which shows the locations for the 6um, 8um and 10um melt
setting conditions.
Also, it was found that the intermetallic compound (IMC)
thicknesses varied on the MBD interconnect. Figure 10
shows a 2.1- 2.8um IMC thickness range at the solder to Cu
pillar interface whereas only a 1.2um IMC thickness at the
solder to ITP pad interface. This can be explained by the
fact that the solder capped Cu-pillar saw two reflows
whereas the ITP pad saw just one solder reflow. The
amount of IMC on the die side prior to assembly was
approximately 1um.
300C
Head
Twice reflowed
(1.Solder
Target: <3um
One reflow
time reflow
130C
Stage
Figure 10. IMC thickness variation
on the top and bottom
of the MBD interconnection.
As mentioned previously, the goal was to develop a process
having a MBD interconnect nominal height of around 35um
and having no solder bridges or opens. Figure 11 shows the
details of DOE2.
Stage Temp
150C
Hold time
1sec
Future Process
Window Investigation
140C
130C
3sec
Current Process Window
Melt setting 6um
8um
10um
5sec
12um
DOE2: TCB BONDING PROCESS WINDOW
VALIDATION
In order to validate the best process window conditions
derived from DOE1, a set of 36 interposers were assembled
using the process conditions shown in Table 4. From this
build 33/36 parts passed electrical test with no solder
defects.
Bonding Conditions:
•
•
Gap Control = -10um
Flux Type/Dip = ABC / 5um
•
Force = 2.8N
•
•
•
•
Stage Temp = 130C
Contact Temp = 130C
Peak Temp/Time = 305C / 5sec
Release Temp = 130C
91.7% MBD Yield: 33/36 MBD Passed e-test “Good” ITP
Table 4. Build conditions to validate DOE2 process
window.
Moreover, after careful failure analysis of the 3 parts
showing electrical test open failures, it was determined that
all three were due to opens in the RDL trace in the MBD
daisy chain. Figure 13 shows an SEM image of the open in
the trace on the MBD side. When this open defect was
compared with a good interconnect, it was found that the
good interconnect had no metallization defects, explaining
why these 3 assemblies failed.
Figure 11. DOE2–Process window definition
A melt setting of 12um resulted in solder bridging. Only a
melt setting of 10um yielded a nominal joint height of about
32um without any opens or bridges. Figure 12 shows a
comparison of the nominal MBD interconnect heights when
a melt setting of 6um and 10um was used. For the 6um melt
setting a nominal joint height of 42.6um was achieved, and
for a 10um melt setting a nominal joint height of 31.8um
was achieved.
Melt Setting 6um
42.6um
Open Unit
Melt Setting 10um
31.8um
Figure 12. Comparison of MBD nominal joint heights, melt
settings of 6um and 10um using DOE2.
Figure 13. SEM image showing open defect in the trace.
DOE3: Impact of Flux on MBD Integrity
Some parts built with flux A that passed electrical test after
MBD attach and underfill showed electrical failure after the
ITP- to-substrate assembly process. Cross-section and SEM
examination of the failed parts showed non-setting at the
solder to ITP bonding pad interface (Figure 14). Weak flux
activity was suspected to be the root cause of the failure.
In DOE3, we evaluated the effect of two different flux
materials, Flux A and Flux B, on interconnect integrity.
Flux B has higher activity and also leaves very low residue.
MBD to the ITP joint after the ITP had been assembled to
the substrate through a conventional solder reflow process.
Table 5 shows the bonding conditions used for DOE3,
which were the optimized conditions from DOE1 and
DOE2. Three different flip chip reflow profiles were
investigated: 130s, 90s and 60s as time above liquidus
(TAL). In the conditions using Flux A, only the parts using
130s TAL showed complete MBD integrity. Both the 90s
and 60s TAL showed failures in the MBD solder
interconnect.
Figure 15. SEM image showing good MBD integrity after
bonding using Flux B
All parts built using Flux B showed good MBD joint
integrity after post flip chip reflow and cleaning. Figure 15
shows an intact MBD interconnect using Flux B. This
image was representative of all three TAL conditions.
Therefore Flux B was chosen as the POR material for the
TCB bonding. Figure 16 shows a representative CSAM
image of the underfilled MBD in which there are no voids
after curing the underfill material
Figure 14. SEM image of a part build using flux A showing
non-wetting at the solder to ITP pad interface.
Stage
Temp
(C)
Contact
Temp(C)
Peak
Temp
Release
Temp(C)
Contact
Force(N)
Melt Setting
(um)
130
130
305C
for
5sec
130
2.8
10
Table 5. Optimal MBD bonding conditions used for DOE3
Figure 16. CSAM image of MBD after assembly using Flux
B, 90s TAL.
Table 6 shows summary of DOE3 results. From this testing
one can see that the POR flux material passed all three TAL
conditions. In addition the parts built with Flux B were
subjected to an additional TST for 200 cycles and did not
show after failure.
Table 6. DOE3 Results Summary of the results
16 parts built using Flux B (POR) were subjected to MSL
Level 3 pre-conditioning and 3X solder reflow per JEDEC
standard. All 16 units tested passed MSL Level 3 test. The
parts were further subjected to 200 cycles of thermal shock
from -55C to 125C. All 16 units passed the test.
DISCUSSION
The main focus of this assembly process development was
to establish an assembly process window that was
compatible with OSAT assembly facility. In this approach a
Si-to-Si bonding of the solder capped Cu-pillars on the
MBD was done to a non-bumped Si-ITP using thermal
compression bonding. The challenge was to create the right
process conditions that can produce a high yield with no
solder bridges or opens.
As can be seen from the
experimental flow, first we experienced solder bridging.
Once the solder bridging was eliminated using the
conditions of DOE1 Task 1, the next goal was to eliminate
the solder opens, which was the objective of Task 2. From
Task 2, solder opens were eliminated, however, the nominal
solder interconnect height was about 43um, which was
higher than the target of 35um.
In DOE1 Task 2, the melt setting was varied and it was
determined that a value of 10um produced no solder opens.
This was based on bonding 70 die in which we achieved a
90% assembly yield, in which the remaining 10% failures
were due to cracked traces on the micro bumped die (as
shown in Figure 13). Also, from this work, we were able to
plot the gap height versus melt setting and determine the
best condition to achieve a nominal interconnect height of
35um. Figure 17 shows a linear regression plot of the gap
height versus melting setting from this particular build.
These are single measurement points made at the same
location, which is the center of the micro bumped die.
are very confident in achieving a process window that can
produce a high yield MBD to Si-ITP assembly yield.
CONCLUSIONS
1. A 2.5D assembly process using a substrate-last
assembly flow has been developed at Invensas and
demonstrate high assembly yield for MBD to SiITP attachment
2. Proper flux selection was critical for the
microbump solder joint integrity and moisture
reliability.
3. The process flow is OSAT friendly and can enable
leverage of existing manufacturing infrastructure at
the OSAT to meet high volume demand for future
2.5D and 3D assembly.
.
ACKNOWLEDGEMENTS
The authors would like to acknowledge the help and support
of the engineering team at the company. Special thanks are
extended to Bong-Sub Lee, KM Bang, Grant Villavicencio,
Hala Shaba, Roseann Alatorre and Gabe Guevara for their
engineering work in design, assembly and characterization.
REFERENCES
1. B. Banijamali, S. Ramalingam, K. Nagarajan and
R.Chaware, “Advanced reliability study of TSV interposers
and interconnects for the 28nm technology FPGA,” ECTC
2011, IEEE 61st, May 31 – June 3, 2011, pp. 285-290.
2. J. Lannon, A. Hilton, A. Huffman, M. Butler, D. Malta,
C. Gregory, D. Temple, “Fabrication and testing of a TSVenabled Si Interposer with Cu and Polymer-based multilevel
metallization,” CPMT, IEEE Transactions Vol. 4, Issue 1,
Jan 2014, pp. 153-157.
3. P. Garrou, M. Koyanagi and P. Ramm, “Handbook of
3D Integration – 3D Process Technology,” Vol.3, 2014
Wiley-VCH Verlag GmbH & Co, Weinheim, Germany, pp
8-9.
4. C.-P.Yeh, I. C. Ume, R. E. Fulton, K.W.Wyatt, and J.W.
Stafford, “Correlationof analytical and experimental
approaches to determine thermally induced PWB,” IEEE
Trans. Comp., Hybrids, Manufact. Technol., vol. 16, pp.
986–995, Aug. 1993.
5. M. R. Stiteler, I. C. Ume, and B. Leutz, “In-process
board warpage measurement in a lab scale wave soldering
oven,” IEEE Trans. Comp., Packag., Manufact. Technol. A,
vol. 19, pp. 562–569, Dec. 1996.
Figure 17. MBD gap height versus melt setting from DOE1
Task 2 build.
The goal of DOE2 was to validate the best process window.
Here the goal was to achieve a nominal interconnect height
of about 35um without defects. As shown from Table 4
there were 3/36 assemblies with opens which were due to
defects in the MBD metallization. Based on this work we
6. D. B. Rao and M. Prakash, “Effect of substrate warpage
on the second level assembly of advanced plastic ball grid
array (PBGA) packages,”in Proc. 21st IEEE Int. Electron.
Manufact. Technol. (IEMT) Symp.,Austin, TX, Oct. 13–15,
1997, pp. 439–446.
7. T. Lee, J. Lee, and I. Jung, “Finite element analysis for
solder ball failures in chip scale packages,” Microelectron.
Rel., vol. 38, no. 12, pp., 1941–1947, 1998.
8. G. Gao, S. McGrath, B. Lee, C. Uzoh, G. Villavicencio,
H. Shaba, L. Wang, S. Arkalgud and E. Tosaya” Addressing
Critical Assembly Challenges in 2.5D and 3D IC
Assembly”, IWLPC, Nov. 2014, San Jose, CA
9. C. G. Woychik, L. Wang, S. Arkalgud, G. Gao, A. Cao,
H. Shen, L. Mirkarimi, E. Tosaya, “Scalable approaches for
2.5D IC assembly,” Chip Scale Review, July-August 2014,
pp. 20-24.