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For Immediate Release
Tip Sheet For
2015 IEEE International Electron Devices Meeting (IEDM)
The IEEE’s annual IEDM conference (www.ieee-iedm.org) is the world’s premier forum for
scientists and engineers in the field of micro and nanoelectronics to present research breakthroughs. This
Tip Sheet is an advance look at some of the most newsworthy topics and papers to be presented at the
61st annual meeting, to be held at the Washington, D.C. Hilton from December 7-9, 2015. Please contact
us to schedule press interviews with IEDM spokespeople and/or with paper authors.
**** Definitions of acronyms and technical terms are on pages 8-9 ****
A) Memories
DRAMs Poised for 20nm and Below: Further advancement in dynamic random access memories
(DRAMs) has all but been given up for dead time and time again, as scaling them gets more difficult and
as alternative memory technology options proliferate. Now that leading-edge technology is at 20nm and
below that day might finally seem to be at hand, but designers keep coming up with new tricks to extend
their usefulness. The trend will continue at the IEDM when Samsung researchers describe clever
techniques they used to wring substantial performance improvements out of state-of-the-art 20nm
DRAMs with no need for expensive and as-yet unproven fabrication techniques like EUV lithography.
One key improvement is a honeycomb cell structure that effectively increases cell pitch by 7.5%,
leading to a 57% increase in cell capacitance for improved data retention. Another is an air-gap spacer
arrangement that achieves a 34% reduction in bitline capacitance for faster operation. The researchers
say these techniques will be key enablers for DRAMs for the 20nm node and beyond. (Paper 26.5, 20nm
DRAM: A New Beginning of Another Revolution; Jemin Park et al, Samsung)
New NAND Architecture: The most popular 3D NAND architectures are gate-all-around (GAA)
devices arranged in a vertical channel structure. While these exhibit excellent device performance, they
are highly sensitive to any variations in their critical dimensions (CD). It is increasingly difficult to
maintain precise dimensional control of these structures at the high aspect ratios required, however.
Macronix researchers will describe an alternate 3D NAND architecture that mitigates this issue. Their
IEDM 2015 Tip Sheet/ page 2
idea is to create a 2D-like structure but in the vertical direction; i.e., to stand it up on its end, in effect.
The structure is a single-gate, flat-cell thin film transistor (TFT) with an ultra-thin body that Macronix
calls single-gate vertical channel (SGVC). The design is not as sensitive to CD variation and the
researchers say it can have potentially more than four times the memory density of GAA vertical
channels at the same scaling node. (Paper 3.2, A Novel Double-Density, Single-Gate Vertical Channel (SGVC) 3D
NAND Flash That Is Tolerant to Deep Vertical Etching CD Variation and Possesses Robust Read-disturb Immunity; HangTing Lue, Macronix)
Making RRAM with a FinFET and Its Dielectric: A research team led by Taiwan’s National TsingHua University will describe a novel way to build a resistive memory (RRAM): use a FinFET transistor
for the “select” gate and the FinFET’s HfO2-based resistive dielectric film for a storage node of the
RRAM cell. At the 16nm node, the RRAM cell size is 0.07632μm2 without any additional mask or
process steps required. It exhibits low-voltage operation, good retention and excellent reliability overall.
(Paper 10.5, 1Kbit FINFET Dielectric (FIND) RRAM in Pure 16nm FinFET CMOS Logic Process; Hsin Wei Pan et al,
National Tsing-Hua University/Taiwan Semiconductor Manufacturing Co.)
B) Alternatives to Silicon
III-V Nanowire CMOS on Silicon: High electron-mobility III-V semiconductors have been intensely
researched as alternative channel materials for sub-7 nm technology nodes, but one of the main
stumbling blocks is how to integrate them monolithically and cost-effectively with traditional CMOS
silicon technology. A team led by National University of Singapore will describe the first use of
vertically stacked III-V nanowires to do so. The key was an extremely thin (sub-150nm) high-quality
GaSb buffer layer on silicon. On top of it, the researchers built multi-gate InAs nFETs and GaSb pFETs
from stacked InAs or GaSb nanowires, respectively. The fabrication technique employed multiple
common modules such as gate stack and contact processes. Good subthreshold slope of 126 mV/decade
and DIBL of 285 mV/V were obtained for the InAs nFET with a 20nm channel length. Meanwhile, the
lowest reported subthreshold slope of 188 mV/decade and the highest reported Ion/Ioff ratio of 3.5 were
demonstrated for the GaSb pFET, which had a channel length of 500nm. The technology may be
suitable for future high-performance and low-power logic applications. (Paper 15.4, Gate-All-Around CMOS
(InAs n-FET and GaSb p-FET) Based on Vertically-Stacked Nanowires on a Si Platform, Enabled by Extremely-Thin Buffer
Layer Technology and Common Gate Stack and Contact Modules; Kian-Hui Goh et al, National University of
Singapore/Nanyang Technological University)
Diamond-Shaped Ge Nanowire FETs: Silicon and germanium have crystalline atomic structures
which, like other crystals, have different facets. The materials’ electrical properties can vary according
to which facet is used to build devices, and some facets are more favorable than others. A team led by
Taiwan’s National Nano Device Laboratories will describe how they built gate-all-around (GAA)
nanowire MOSFETs with diamond-shaped Ge and GeSi nanowire channels. The purpose of the work
was to find a way to more effectively use germanium (Ge) as the channel material in multi-gate device
configurations, because high-mobility Ge is seen as potentially necessary for scaling beyond the 10-nm
technology node. Using common dry etching and blanket epitaxy techniques, the researchers sculpted
Ge and GeSi nanowires into diamond cross-sectional shapes, with four favorable facets (the so-called
{111} orientation) exposed. They used these nanowires as suspended channels in a GAA MOSFET
configuration. Both nFET and pFET transistors with excellent performance were demonstrated,
including pFETs with an Ion/Ioff ratio exceeding 108, the highest ever reported for Ge-based pFETs. (Paper
15.1, Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch
IEDM 2015 Tip Sheet/ page 3
Technology; Yao-Jen Lee et al, National Nano Device Laboratories/National Chiao Tung University/National Chi Nan
University)
High-Frequency, Low-Leakage IGZO Transistors for Internet of Things: Much work is ongoing to
develop low-power devices and circuits for Internet of Things applications. A team from Japan’s
Semiconductor Energy Laboratory Co. will describe how they made 20nm gate-all-around MOSFETs
with incredibly low off-state currents of <0.1pA, yet with cutoff frequencies exceeding 10GHz. The
transistors were made from thin films of indium-gallium-zinc-oxide (IGZO). They were built using a
self-aligned process that eliminated overlaps from the gate to the source and drain, rendering the channel
immune from short-channel effects that otherwise would degrade performance. Integrated in a DRAM
memory cell to demonstrate their performance, their extremely low off-current allowed for data
retention of >10 days at 125°C. (Paper 6.5, 20-nm-node Trench-Gate-Self-Aligned Crystalline In-Ga-Zn-Oxide FET
with High Frequency and Low Off-State Current; Daisuke Matsubayashi et al, Semiconductor Energy Laboratory Co., LTD)
InGaAs Nanowire FETs on Silicon: There have been many demonstrations of the potential
performance benefits of III-V channels for low-power logic devices, but complete integration of these
channels in devices made on standard 300mm silicon wafers would demonstrate their manufacturability
and relevance to the industry. That day is getting closer, as a team led by Imec will discuss gate-allaround, high-performance InGaAs nanowire MOSFETs built on 300mm silicon wafers. Their high
transconductance (gm=2200) indicates that despite having a lattice-mismatched substrate, the InGaAs
channel material maintains its high carrier velocity. (Paper 31.1, Gate-All-Around InGaAs Nanowire FETS with
Peak Transconductance of 2200 μS/μm at 50nm Lg Using a Replacement Fin RMG Flow; N. Waldron et al, Imec/ASM)
C) 3D Devices & Circuits
Monolithic 3D Chip: 3D circuits often are made by stacking separate chips and connecting them
electrically with through-silicon vias (TSVs), but TSVs have significant disadvantages including
relatively narrow I/O bandwidth. Monolithic 3D ICs with no TSVs—where the devices in adjacent
layers are directly connected—have been demonstrated, but transistor damage from thermal annealing
can arise. That’s because each layer in a 3D device must be annealed to remove stresses in its crystalline
silicon structure, and also to activate the dopants which have been implanted in it. However, the high
heat involved with annealing (>1,000°C) can damage the devices that have already been built in lower
layers. A team led by Taiwan’s National Nano Device Laboratories addressed this issue by using a CO2
far-infrared laser at 400°C to selectively pulse-anneal specific areas of the silicon (the source-drain
regions). They used this technique to build a sub-40nm monolithic IC containing a variety of
heterogeneous functions—logic, SRAM, RRAM, sense and analog amplifiers, and gas sensors. No
device degradation was reported, and the researchers say their technique is suitable for making the lowpower, low-cost, small-footprint and heterogeneously integrated devices needed for the Internet of
Things. (Paper 25.4, Low-Cost and TSV-free Monolithic 3D-IC with Heterogeneous Integration of Logic, Memory and
Sensor Analogy Circuitry for Internet of Things; Tsung-Ta Wu et al, National Nano Device Laboratories/National Tsing Hua
University)
D) Power Devices
Better GaN HEMTs for High-Power Amplifiers: High electron-mobility transistors (HEMTs) made
from GaN have great potential for use in high-power millimeter-wave amplifiers for high-data-rate
wireless networks. Normally these transistors use an InAlN barrier layer to separate the channel from the
IEDM 2015 Tip Sheet/ page 4
source and drain. However, a team led by Fujitsu will show that InAlN is inadequate for devices
intended for use in high-power amplifier applications because it facilitates “current collapse,” where a
collection of electron traps occurs and alters the device’s performance. Instead, they used a higherquality barrier material, InAlGaN. They also employed a novel double-layer SiN passivation technique.
The 80nm-channel-length InAlGaN/GaN power HEMTs they built demonstrated a record 3 W/mm
output power density at 96 GHz, which is a 60% improvement over the best results reported to date.
Reliability also was superb. The power and reliability performance put the HEMTs at the state-of-the-art
for use in W-band amplifiers (75–110 GHz). (Paper 9.1, Collapse-Free High Power InAlGaN/GaN-HEMT with 3
W/mm at 96 GHz; K. Makiyama et al, Fujitsu/Tokyo Institute of Technology)
E) Silicon Photonics
CMOS-Compatible Laser: Silicon photonics is an evolving technology in which light, not wires,
carries data within and among computer chips. Light can carry more data, faster, using less power than
metal wires. Silicon is ubiquitous in electronics but it is a poor material for light-emitters like lasers, and
the integration of lasers made from other materials into standard silicon CMOS devices is problematic.
But if that could be done more easily, then much more powerful computers and other digital systems
could be built. A research team from several European research organizations and universities, led by
Germany’s Forschungszentrum Jülich institute, will report on a silicon-based direct-bandgap
germanium-tin (GeSn) micro-disk laser that emits at a lasing wavelength of 2.5 μm at a power output of
221 kW/cm2. The device was built using standard CMOS-compatible processing and was monolithically
integrated on a silicon platform. Its 560-nm-thick GeSn epitaxial layers were grown on Ge buffers/Si
substrates. Its lasing performance arises from 1) straining the epitaxial layers so they become direct
bandgap materials; and 2) its micro-disk cavity architecture. The work is an important step toward
integrated silicon photonics. (Paper 2.6, Direct Bandgap GeSn Microdisk Lasers at 2.5 µm for Monolithic Integration
on Si-Platform; Stephan Wirths et al, Forschungszentrum Jülich/ Paul Scherrer Institute/ETH/University of Leeds/University
of Grenoble/CEA LETI Minatec)
F) Physically Flexible Electronics
RF CMOS Circuits on Flexible, Application-Specific Substrates: Although physically flexible
circuitry would enable innovative wearable, biomedical, security and other products, flexible circuits so
far have demonstrated only limited performance. That’s because high-performance CMOS devices are
fabricated using harsh high-temperature processes that damage most flexible materials. A team led by
France’s Institut d’Electronique de Microélectronique et de Nanotechnologie, though, has developed
what they call an ultimate thinning and transfer-bonding (UTTB) process which they used to build
radio-frequency CMOS circuits on a variety of flexible substrates: polyimide plastic film, glass, and
stainless steel. First they built RF CMOS circuits on an SOI substrate, then they thinned it to 30µm by
completely removing the backside. The circuits were then transferred to the various substrates using a
laminating process. For plastic and glass substrates, the circuitry was attached by laminating it using a
dry polymer film and rollers. For stainless steel substrates, a 400nm–thick indium layer was first
deposited, and then the circuits were laminated to it in a similar manner. The small-signal performance
of these devices wasn’t significantly degraded from what it had been on the original substrate, and
unwanted harmonics were actually reduced. The researchers say their UTTB technique can be adapted
to meet application-specific requirements for ultra-mechanical flexibility, heat dissipation and
transparency. (Paper 15.7, Application-Oriented Performance of RF CMOS Technologies on Flexible Substrates; Justine
Philippe et al, IEMN/STMicroelectronics/CEA LETI Minatec)
IEDM 2015 Tip Sheet/ page 5
Flexible Circuits Built from 2D Nanomaterials: Crystalline materials consisting of a single layer of
atoms are referred to as two-dimensional (2D) materials. A University of Texas team will present an indepth look at the prospects for flexible electronics based on 2D materials such as graphene, phosphorene
and transition metal dichalcogenides (TMDs). The authors will describe how in a wide range of
experiments they achieved high performance from these nanomaterials on flexible substrates. Target
applications, which could include wearable devices and Internet-of-Things components, cover a large
frequency spectrum encompassing low-power RF, microprocessors, transceivers and THz electronics.
The authors suggest that the large number of available 2D materials with vastly different physical
properties will allow custom designing of circuit functions tailored to specific applications. They
envision flexible nanosystems built from the heterogeneous integration of semiconducting, semimetallic
and insulating 2D materials. (Paper 32.1, High-Frequency Prospects of 2D Nanomaterials for Flexible Nanoelectronics
from Baseband to Sub-THz Devices; Saungeun Park et al, University of Texas at Austin)
G) Displays & Imaging
Multiband Imaging in One Device: There is a growing demand for integrated imaging systems that
can simultaneously capture both red-green-blue (RGB) visible light and near-infrared (NIR)
wavelengths that contain range-finding, or depth-of-field, information. In medicine, for example, the
ability to capture all of these wavelengths simultaneously with one compact device would make it easier
and less time-consuming to identify and pinpoint a wide range of targets in different parts of the body,
such as pathological lesions. Until now, however, trying to detect both RGB and NIR signals on the
same chip would compromise either one or the other. Researchers at Olympus will detail how they used
3D wafer-stacking technology to integrate two separate CMOS imagers into one device, each optimized
for either RGB or NIR through a careful balance of active silicon thickness and pixel size. The top
imager is optimized for visible detection with an array of small pixels and a thinned 3µm active silicon
layer. NIR signals pass through it to reach the bottom imager, which is optimized for NIR detection with
an array of larger pixels and thick active silicon. The researchers say there is no degradation in color
reproduction, sensitivity or resolution. (Paper 30.1, Multi-Storied Photodiode CMOS Image Sensor for Multiband
Imaging with 3D Technology; Y. Takemoto et al, Olympus)
H) Brain-like Computing
Artificial Synapses for Learning: Advances in machine learning and neuroscience have sparked
growing interest in neuromorphic (brain-inspired) computing, and a number of neuromorphic circuits
have been demonstrated that are capable of functions such as pattern-recognition. At the IEDM, IBM
researchers will describe a chip that may bring neuromorphic computing closer to true artificial
intelligence: the largest neuromorphic “core” ever built, a 256 x 256 array of artificial synapses with onchip programming circuitry. It may be capable of “deep learning,” which is when machines follow
sophisticated algorithms in an attempt to mimic brain functions like seeing, listening and thinking. The
synapses are 64k-cell phase-change memory (PCM) devices, and the researchers say that each PCM
synapse is capable of running in one of three modes independently, each of which is an analog of the
behavior of real neurons: 1) so-called leaky-integration-and-fire (the synapse fires when input voltage
reaches a certain threshold); 2) spike-timing dependent plasticity (an algorithm that mimics a
fundamental brain mechanism for learning and memory; and 3) in idle mode. The researchers say that
once wiring issues are solved the array size potentially could be increased to the biological scale. (Paper
17.1, NVM Neuromorphic Core with 64k-cell (256-by-256) Phase Change Memory Synaptic Array with On-Chip Neuron
Circuits for Continuous In-Situ Learning; S. Kim et al, IBM)
IEDM 2015 Tip Sheet/ page 6
I) Noteworthy Papers on Diverse Topics
Vacuum Nanoelectronics Integrated with Silicon: Vacuum electronics technology may sound like
ancient history but a team from MIT has used a modern variant to make some very futuristic devices.
They are nanoscale cold cathodes (tiny electron guns) built from arrays of nanowire field emitters that
can be integrated with traditional silicon technology. The integrated devices may enable compact new
RF amplifiers and sources of terahertz, infrared and X-ray energy. They combine the positive aspects of
solid state semiconductors (high gain and low noise) with those of vacuum electronics (high power and
efficiency). They demonstrated a current density of >100 A/cm2, more than a hundredfold greater than
any other field-emission cathode operated in continuous wave mode. At the same time, the devices also
exhibited long lifetimes and low-voltage operation. Each emitter (6-8nm tip diameter) sits atop a vertical
silicon nanowire (10µm tall, 100-200nm in diameter). The nanowire acts as a current limiter to protect
the emitter from possible damage from heating and arcing. The team built emitter arrays as large as
1,000 x 1,000. (Paper 33.1, High Performance and Reliable Silicon Field Emission Arrays Enabled by Silicon Nanowire
Current Limiters; Stephen Guerrera et al, MIT)
Moore’s Law in Neural Science? Optogenetics is a technology used to study neurons by interacting
with them using visible light to stimulate their constituent proteins. The neural cells aren’t damaged, as
they can be when electrically stimulated. A team led by Imec will discuss an implantable neural probe
that has the highest reported density of optrodes (light emitters) and electrodes (to record the responses
of the neurons once they are stimulated). As with CMOS digital devices, neural probes benefit from high
integration densities, which are enabled by decreasing feature sizes. Higher density leads to better spatial
resolution and also enables smaller probes that are less likely to damage tissue. To build the probe, the
researchers integrated two different CMOS processes (silicon nitride photonics and TiN electrodes).
They built probes 100µm wide and 30µm thick, containing 12 optrodes (6 x 20 µm2 in size) and 24
electrodes (10 x 10 µm2). They packaged the circuitry, implanted it in a mouse brain and successfully
demonstrated that it could both drive and record neural activity. (Paper 29.5, High Density Optrode-Electrode
Neural Probe Using SixNy Photonics for In Vivo Optogenetics; Luis Hoffman et al, Imec/KU Leuven)
3D Views of Nanoscale Devices: Two noteworthy IEDM papers will describe different ways to
generate highly accurate 3D views of extremely small devices, as an aid to ultimately boosting their
performance:
 3D Maps of TFET Heterojunctions: Tunneling field-effect transistors (TFETs) are an
emerging technology based on principles of quantum mechanics. TFETs are promising for ultralow-power applications but improvements in their performance and reliability are needed.
Critical to TFET performance when they are made from combinations of III-V materials is the
need for abrupt and uniform interfaces among the dissimilar materials. Variability at these
interfaces, or heterojunctions, reduces device performance. It is difficult to characterize
heterojunctions with precision in nanometer-scale devices, but a Penn State team used atom
probe tomography and time-of-flight spectroscopy to do so. First they cooled TFET samples to
50° Kelvin. Then, they rapidly heated the heterojunction under study with laser pulses to
evaporate layers of atoms from it, one layer at a time. They captured the atoms from each layer
in an electric field, and then performed spectroscopic analysis to identify the individual atoms
which constituted each layer. From all this data they built a 3D map of the heterojunction, with a
resolution of 2.4nm. They also studied two other sources of variability in TFETs—random
dopant fluctuations and the interface between the channel and the ultra-thin high-k gate
IEDM 2015 Tip Sheet/ page 7
dielectric—with an eye toward further improvements. (Paper 14.2, Tunnel Junction Abruptness, Source
Random Dopant Fluctuation and PBTI Induced Variability Analysis of GaAs0.4Sb0.6/In0.65Ga0.35As
Heterojunction Tunnel FETs; R. Pandey et al, Pennsylvania State University)

3D Carrier Profiling in 10nm FinFETs: In solid state devices, electrons and holes are
generically called charge carriers. As 3D devices such as FinFETs scale to the 7nm and 5nm
nodes, fewer charge carriers are available. Because their distribution is not uniform, it becomes
critical to establish correlations between their actual locations within the 3D architecture and the
device’s electrical performance. Once these correlations are known, the architecture can be
modified for better performance. Scanning Spreading Resistance Microscopy (SSRM) is a
technique that uses a probe to measure a surface’s electrical resistance and thus the density of
charge carriers at any given point on the surface. An Imec team will discuss a variation of the
technique they call Scalpel SSRM, which uses diamond-based probe tips to scrape off material
as the surface is repeatedly scanned on all sides, thus probing deeper into the material layer by
layer. They used the resulting data to produce accurate 3D maps of the density of charge carriers
throughout sub-10nm FinFETs. They say their existing technique can be used to profile carrier
density in 3D devices as small as 4nm, and that it has the potential to achieve a resolution of just
1nm, which would make it useful for characterizing extremely small future architectures such as
gate-all-around arrangements and nanowires. (Paper 14.1, Scalpel Soft Retrace Scanning Spreading
Resistance Microscopy for 3D-carrier profiling in sub-10nm WFIN FinFET; Pierre Eyben et al, Imec)
Better Modeling of STT-MRAMs: Spin-transfer-torque magnetic random access memory (STTMRAM) is a promising technology for future non-volatile, high-speed applications. But the internal
magnetic dynamics of this new and complex technology aren’t completely understood, which poses a
hurdle to optimizing and commercializing it. Computer modeling and simulation of STT-MRAMs is
essential for a better understanding. However, until now building such complex models for circuit
simulation has been laborious, time-consuming and prone to inaccuracy because it has relied on fitting
to data from sample devices. Samsung researchers developed a simpler, more accurate computer
modeling framework built from the essential physics. It enables the study of all possible magnetic
interactions involved in the switching of the devices’ ferromagnetic layer, as well as charge transport
and spin transfer torque interactions in magnetic tunneling junctions. The researchers verified the
accuracy of their model by comparing it with actual data from 15nm STT-MRAMs. Their work will lead
to better simulations of circuits and systems which incorporate these state-of-the-art devices. (Paper 28.5,
Physics-Based Compact Modeling Framework for State-of-the-Art and Emerging STT-MRAM Technology; Nuo Xu et al,
Samsung)
Atom-by-Atom Modeling of Grain Boundaries: Future flash memories may be stackable devices with
polysilicon channels running vertically through them. However, defects in polysilicon’s crystal structure
called grain boundaries decrease electrical conductivity by scattering and trapping electrons. A good
understanding of the actual conduction paths in these channels would enable more accurate predictions
of how the devices will operate. Existing computer models of these paths, though, are based on
generalized assumptions about grain boundaries. An Imec team will present a new atomistic 3D model
of grain boundaries that takes into account specific regions of enhanced scattering in the polysilicon,
plus specific charge defects that can cause local barriers and depletion areas. The model gives statistical
insight into the properties of scaled poly-Si channel devices (particularly vertical NAND devices), and
their yield and reliability limitations. (Paper 5.6, Statistical Poly-Si grain boundary model with discrete charging
defects and its 2D and 3D implementation for vertical 3D NAND channels; Robin Degraeve et al, Imec)
IEDM 2015 Tip Sheet/ page 8
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Here are definitions of some important technical terms you may find useful:
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Back-End/BEOL and Front-End/FEOL -- In integrated circuit manufacturing, transistors and other active devices
are built first (at the front end of the manufacturing line or FEOL), while the interconnect, or the wiring, is built
afterward, at the “back end” of the manufacturing line (BEOL).
Carbon nanotube (CNT) – A cylinder made of carbon atoms, measured in nanometers (nm).
CMOS/MOS/MOSFET/FET-- Most transistors today are FETs, or field-effect transistors. Most FETs are built
with CMOS manufacturing technology (complementary metal oxide semiconductor). Generically they are called
MOSFETs, or sometimes MOS transistors.
Compound/III-V Semiconductors -- Most semiconductors are silicon-based, but researchers continue to
investigate other semiconducting materials with higher electron mobilities because they can be used to make faster
devices. The tradeoff is that the materials are harder to work with than silicon. Compound semiconductors are made
of two or more elements (e.g. GaAs, InP, GaN, etc.) that are generally found in groups III and V of the periodic
table of the elements.
DIBL -- Drain-induced barrier lowering is a parasitic short-channel effect in MOSFETs that influences threshold
voltage.
Electromigration -- A serious reliability issue. At tiny dimensions some materials tend to physically move when
current flows through them, leading to voids, gaps or outright breaks in what should be a uniform material.
Electron mobility -- A measure of the velocity of electrons in a semiconductor.
FinFET -- A transistor whose shape resembles a fin, usually with multiple gates surrounding it for better on/off
control.
ft -- a measure of transistor speed known as unity current gain cutoff frequency, above which the device loses its
amplifying capability.
fmax -- a measure of transistor speed denoting its maximum oscillation frequency
Front-End/FEOL and Back-End/BEOL -- In integrated circuit manufacturing, transistors and other active devices
are built first (at the front end of the manufacturing line or FEOL), while the interconnect, or the wiring, is built
afterward, at the “back end” of the manufacturing line (BEOL).
HEMT -- A HEMT, or high-electron-mobility transistor, is a field-effect transistor with a channel built from a
sandwich of two materials with different energy band gaps, instead of a channel built from doped silicon as is the
case with most MOSFETs. HEMTs operate at higher frequencies than ordinary transistors, up to millimeter-wave
frequencies, and are used in high-frequency products such as cell phones, satellite television receivers, voltage
converters, and radar equipment.
High-k Dielectrics/Metal Gates -- A dielectric is an insulator. “k” is a measure of how well a material will work as
a dielectric. A higher numerical value for “k” means better insulating performance without increased physical
thickness of the insulating layer. For the gate of a transistor, which turns it on and off, a high-k dielectric is critical
because if current leaks through the gate, the transistor won't work properly. In the past gates were usually made of
polysilicon with an oxide dielectric, but these are not scalable to meet the needs of the latest technology generations.
Other good dielectrics exist but they aren't compatible with polysilicon gates. The latest generations of MOSFETs
use metal gates with high-k dielectrics to enable continued scaling and higher device performance.
III-V -- see Compound/III-V Semiconductors
Integrated Circuit -- A tiny electrical circuit built on a semiconducting substrate.
Internet of Things -- The idea of giving everyday objects network connectivity, allowing them to send and receive
data.
Lithography/Photolithography/EUV Lithography -- Transistors are built on chips using photolithography, a
process by which light is shone through a patterned photomask onto a chip’s surface. The light transfers a copy of
the image on the mask to a light-sensitive layer on the chip’s surface, in much the same way the image on a
photographic negative is transferred onto photo paper. The chip’s surface is then engraved with chemical etches and
other treatments in order to build the patterned devices and circuits. Right now various tricks and tweaks enable us
to build transistors smaller than the wavelength of light used to pattern them. But for future technology generations
of ultra-small transistors, the shorter wavelengths of extreme ultraviolet light (EUV) may be needed. Researchers are
working to develop cost-effective, high-throughput EUV systems.
IEDM 2015 Tip Sheet/ page 9
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Low-k Dielectrics/Interconnect -- Interconnect refers to the copper lines that connect devices on a chip. The tiny
widths and close proximity of adjacent lines introduce resistance and capacitance delays that can hinder chip
performance. Here a low-k dielectric is needed, to insulate the copper lines while minimizing capacitance increase,
but these materials are fragile and pose many challenges.
MEMS/NEMS -- A micro-electromechanical system/nano-electromechanical system, containing micrometer-scale
moving parts (the former) or nanometer-scale moving parts (the latter).
Multi-chip Modules -- An electronic package containing multiple ICs, other semiconductors and/or other chip
modules.
Moore’s Law -- An observation made in 1965 by Intel’s Gordon Moore, who said that the number of transistors
which can be placed on an integrated circuit doubles about every two years. Subsequent events have proved him
correct but it’s getting harder to do.
N-FET/P-FET or n-channel/p-channel -- All MOSFETs come in two varieties that work together in a
complementary fashion, N and P.
Phase-Change Memory/PCM -- Phase-change materials have crystalline and non-crystalline states that are used to
represent the digits “0” or “1,” the basis of computer memories. Electrical current is used to toggle between the two
states – heat from the current melts the material to change its state.
Scaling/Density/Integration -- Scaling is making transistors and other circuit elements smaller so that more will fit
on a chip. A denser chip has more transistors on it than one which is less dense. Integration is combining circuit
elements on a chip to add more functions at less cost.
Self-Assembly/“Bottom Up” -- A manufacturing method used at the nanometer scale, making use of the fact many
biological systems automatically self-assemble into various molecular or other structures. Self-assembly techniques
imitate these strategies by encoding a desired structure into the shape and properties of the molecules that are used.
This compares to traditional lithography, where the structure is carved out of a block of matter. Self-assembly is thus
referred to as a 'bottom-up' manufacturing technique, as compared to lithography, a “top-down” technique.
Semiconductor -- A material that can be made to conduct or to block the passage of electrical signals, giving the
ability to store and process data.
SOI -- A silicon-on-insulator substrate, used to reduce parasitic capacitance and thereby improve performance
Strained silicon & SiGe stressors -- Silicon is said to be “strained” when its atoms are pulled farther apart or closer
together than normal. Doing so alters the atomic forces that govern the flow of electrons through the silicon,
enabling transistors built with it to operate faster and /or at lower power. The external stressors which impart strain
are materials with slightly different atomic structures than silicon. For example, a common way to strain silicon is to
build a silicon layer on top of a silicon-germanium (SiGe) layer. The silicon atoms will align with the atoms of the
SiGe layer, which lie farther apart.
SRAM -- A type of computer memory (static random access memory) that uses six transistors to store each bit of
information. It can be written to and read from very quickly.
Subthreshold slope (SS) -- A measure of a MOSFET transistor’s current/voltage characteristics. The steeper it is,
the more abruptly the device can turn on and off.
Technology Generations/Nodes -- Production of 22-nm devices by leading companies is established and the
transition to 16nm/14nm is well underway. Beyond that, 10nm technology is expected to enter production by 2017.
Transconductance -- A measure of transistor performance. Transistors with higher levels of transconductance can
amplify signals more efficiently than low-transconductance devices can. Technically, in a transistor it is the ratio of
change in output current to change in input voltage.
Transistor -- A tiny electrical switch that makes electronic systems possible. It has no moving parts and is made
from semiconductors, usually silicon. Transistors can be ganged together by the millions on chips and programmed
to sense inputs, to process information and to deliver outputs.
TSV – Through-silicon via, a vertical electrical connection (i.e. a “via”) that passes through a silicon wafer or die.
TSVs are used to create 3D integrated circuits and packages of stacked microchips.