UNIT – 4
DECIMAL ELECTRONICS
Number System Used in Digital Electronics :- Number
Systems
Most number systems follow a common pattern for writing down the value of a number:
A fixed number of values can be written with a single numerical character, then a new column is
used to count how many times the highest value in the counting system has been reached. The
number of numerical values the system uses is called the base of the system. For example, the
decimal system has 10 numerical characters and so has a base of 10:
0123456789
For writing numbers greater than 9 a second column is added to the left, and this column has 10
times the value of the column immediately to its right.
Because number systems commonly used in digital electronics have different base values to the
decimal system, they look less familiar, but work in essentially the same way.
Decimal, (base 10)
Decimal has ten values 0 to 9. If larger values than 9 are needed, extra columns are added to the
left. Each column value is ten times the value of the column to its right. For example the decimal
value twenty-two is written 22 (2 tens + 2 ones).
Binary, (base 2)
Binary has only two values 0 and 1. If larger values than 1 are needed, extra columns are added
to the left. Each column value is now twice the value of the column to its right. For example the
decimal value three is written 11 in binary (1 two + 1 one).
Octal, (base 8)
Octal has eight values 0 to 7. If larger values than 7 are needed, extra columns are added to the
left. Each column value is now 8 times the value of the column to its right. For example the
decimal value twenty-seven is written 33 in octal (3 eights + 3 ones).
Hexadecimal, (base 16)
Hexadecimal has sixteen values 0 to 15, but to keep all these values in a single column, the 16
values (0 to 15) are written as 0 to F, using the letters A to F to represent numbers 10 to 15, so
avoiding the use of a second column. Again, if higher values than 15 (F in hexadecimal) are
needed, extra columns to the left are used. Each column value is sixteen times that of the column
to its right. For example the decimal value sixty-eight is written as 44 in hexadecimal (4 sixteens
+ 4 ones).
Each of these different number systems works in the same way, it is just that each system has a
different base, and the column values in each system increase by multiples of the base number as
columns are added to the left.
Because this module describes several different number systems, it is important to know which
system is being described. Therefore if there is some doubt which system a number is in, the
base of the system, written as a subscript immediately after the value, is used to identify the
number system.
For example:
1010 represents the decimal value ten. (1 ten + 0 units)
102 represents the binary value two. (1 two + 0 units)
108 represents the octal value eight. (1 eight + 0 units)
1016 represents the hexadecimal value sixteen. (1 sixteen + 0 units)
The System Radix
The base of a system, more properly called the RADIX, is the number of different values that
can be expressed using a single digit. Therefore the decimal system has a radix of 10, the octal
system has a radix of 8, hexadecimal is radix 16, and binary radix 2.
The range of number values in different number systems is shown in Table 1.1.2, Notice that
because the hexadecimal system must express 16 values using only one column, it uses the
letters A B C D E & F to represent the numbers 10 to 15.
The Radix Point.
When writing a number, the digits used give its value, but the number is ‘scaled’ by its RADIX
POINT.
For example, 456.210 is ten times bigger than 45.6210 although the digits are the same.
Notice also that when using multiple number systems, the term ‘RADIX point’ instead of
‘DECIMAL point’ is used. When using decimal numbers, a decimal point is used, but if a
different system is used, it would be wrong to call the point a decimal point, it would need to be
called "Binary point" or "Octal point" etc. The simplest way around this is to refer to the point in
any system (which will of course have its value labelled with its radix) as the RADIX POINT.
Exponents
A decimal number such as 456.210 can be considered as the sum of the values of its individual
digits, where each digit has a value dependent on its position within the number (the value of the
column):
= 456.210
Each digit in the number is multiplied by the system radix raised to a power depending on its
position relative to the radix point. This is called the EXPONENT. The digit immediately to the
left of the radix point has the exponent 0 applied to its radix, and for each place to the left, the
exponent increases by one. The first place to the right of the radix point has the exponent -1 and
so on, positive exponents to the left of the radix point and negative exponents to the right.
This method of writing numbers is widely used in electronics with decimal numbers, but can be
used with any number system. Only the radix is different.
Hexadecimal exponents 98.216 = (9 x 161) + (8 x 160) + (2 x 16-1)
Octal exponents 56.28 = (5 x 81) + (6 x 80) + (2 x 8-1)
Binary Exponents 10.12 = (1 x 21) + (0 x 20) + (1 x 2-1)
When using your calculator for the above examples you may find that it does not like radix
points in anything other than decimal mode. This is common with many electronic calculators.
Floating Point Notation
If electronic calculators cannot use radix points other than in decimal, this could be a problem.
Fortunately for every problem there is a solution. The radix exponent can also be used to
eliminate the radix point, without altering the value of the number. In the example below, see
how the value remains the same while the radix point moves. It is all done by changing the radix
exponent.
102.610 = 102.6 x 100 = 10.26 x 101 = 1.026 x 102 = .1026 x 103
The radix point is moved one place to the left by increasing the exponent by one.
It is also possible to move the radix point to the right by decreasing the exponent. In this way the
radix point can be positioned wherever it is required, in any number system, simply by changing
the exponent. This is called FLOATING POINT NOTATION and it is how calculators handle
decimal points in calculations.
Normalised Form
By putting the radix point at the front of the number, and keeping it there by changing the
exponent, calculations become easier to do electronically, in any radix.
Electronic storage of numbers.
A number written (or stored) in this way, with the radix point at the left of the most significant
digit is said to be in NORMALISED FORM. For example .110112 x 23 is the normalised form of
the binary number 110.112. Because numbers in electronic systems are stored as binary digits,
and a binary digit can only be 1 or 0, it is not possible to store the radix point within the number.
Therefore the number is stored in its normalised form and the exponent is stored separately. The
exponent is then reused to restore the radix point to its correct position when the number is
displayed.
In electronics systems a single binary digit is called a bit (short for Binary DigIT), but as using a
single digit would seriously limit the maths that could be performed, binary bits are normally
used in groups.
4 bits = 1 nibble
8 bits = 1 byte
Multiple bytes, such as 16 bits, 32 bits, 64 bits are usually called ‘words’, e.g. a 32 bit word. The
length of the word depends on how many bits can be physically handled or stored by the system
at one time.
4 Bit Binary Representation
When a number is stored in an electronic system, it is stored in a memory location having a fixed
number of binary bits. Some of these memory locations are used for general storage whilst
others, having some special function, are called registers. Wherever a number is stored, it will be
held in some form of binary, and must always have a set number of bits. Therefore a decimal
number such as 13, which can be expressed in four binary bits as 11012 becomes 000011012
when stored in an eight-bit register. This is achieved by adding four NON SIGNIFICANT
ZEROS to the left of the most significant ‘1’ digit.
Using this system, a binary register that is n bits wide can hold 2n values.
Therefore an 8 bit register can hold 28 values = 256 values (0 to 255)
A 4 bit register can hold 24 values = 16 values (0 to 15.
Demorgan,s Theorem :- Definition of De Morgan’s law:
The complement of the union of two sets is equal to the intersection of their complements and
the complement of the intersection of two sets is equal to the union of their complements. These
are called De Morgan’s laws.
For any two finite sets A and B;
(i) (A U B)' = A' ∩ B' (which is a De Morgan's law of union).
(ii) (A ∩ B)' = A' U B' (which is a De Morgan's law of intersection).
Proof of De Morgan’s law: (A U B)' = A' ∩ B'
Let P = (A U B)' and Q = A' ∩ B'
Let x be an arbitrary element of P then x ∈ P ⇒ x ∈ (A U B)'
⇒ x ∉ (A U B)
⇒ x ∉ A and x ∉ B
⇒ x ∈ A' and x ∈ B'
⇒ x ∈ A' ∩ B'
⇒x∈Q
Therefore, P ⊂ Q …………….. (i)
Again, let y be an arbitrary element of Q then y ∈ Q ⇒ y ∈ A' ∩ B'
⇒ y ∈ A' and y ∈ B'
⇒ y ∉ A and y ∉ B
⇒ y ∉ (A U B)
⇒ y ∈ (A U B)'
⇒y∈P
Therefore, Q ⊂ P …………….. (ii)
Now combine (i) and (ii) we get; P = Q i.e. (A U B)' = A' ∩ B'
Proof of De Morgan’s law: (A ∩ B)' = A' U B'
Let M = (A ∩ B)' and N = A' U B'
Let x be an arbitrary element of M then x ∈ M ⇒ x ∈ (A ∩ B)'
⇒ x ∉ (A ∩ B)
⇒ x ∉ A or x ∉ B
⇒ x ∈ A' or x ∈ B'
⇒ x ∈ A' U B'
⇒x∈N
Therefore, M ⊂ N …………….. (i)
Again, let y be an arbitrary element of N then y ∈ N ⇒ y ∈ A' U B'
⇒ y ∈ A' or y ∈ B'
⇒ y ∉ A or y ∉ B
⇒ y ∉ (A ∩ B)
⇒ y ∈ (A ∩ B)'
⇒y∈M
Therefore, N ⊂ M …………….. (ii)
Now combine (i) and (ii) we get; M = N i.e. (A ∩ B)' = A' U B'
Examples on De Morgan’s law:
1. If U = {j, k, l, m, n}, X = {j, k, m} and Y = {k, m, n}.
Proof of De Morgan's law: (X ∩ Y)' = X' U Y'.
Solution:
We know, U = {j, k, l, m, n}
X = {j, k, m}
Y = {k, m, n}
(X ∩ Y) = {j, k, m} ∩ {k, m, n}
= {k, m}
Therefore, (X ∩ Y)' = {j, l, n} ……………….. (i)
Again, X = {j, k, m} so, X' = {l, n}
and Y = {k, m, n} so, Y' = {j, l}
X' ∪ Y' = {l, n} ∪ {j, l}
Therefore, X' ∪ Y' = {j, l, n} ……………….. (ii)
Combining (i)and (ii) we get;
(X ∩ Y)' = X' U Y'.
Proved
LOGIC GATES :A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs
and one output. At any given moment, every terminal is in one of the two binary conditions low
(0) or high (1), represented by different voltage levels. The logic state of a terminal can, and
generally does, change often, as the circuit processes data. In most logic gates, the low state is
approximately zero volts (0 V), while the high state is approximately five volts positive (+5 V).
There are seven basic logic gates: AND, OR, XOR, NOT, NAND, NOR, and XNOR.
The AND gate is so named because, if 0 is called "false" and 1 is called "true," the gate acts in
the same way as the logical "and" operator. The following illustration and table show the circuit
symbol and logic combinations for an AND gate. (In the symbol, the input terminals are at left
and the output terminal is at right.) The output is "true" when both inputs are "true." Otherwise,
the output is "false."
AND gate
Input 1 Input 2 Output
1
1
1
1
1
The OR gate gets its name from the fact that it behaves after the fashion of the logical inclusive
"or." The output is "true" if either or both of the inputs are "true." If both inputs are "false," then
the output is "false."
OR gate
Input 1 Input 2 Output
1
1
1
1
1
1
1
The XOR ( exclusive-OR ) gate acts in the same way as the logical "either/or." The output is
"true" if either, but not both, of the inputs are "true." The output is "false" if both inputs are
"false" or if both inputs are "true." Another way of looking at this circuit is to observe that the
output is 1 if the inputs are different, but 0 if the inputs are the same.
XOR gate
Input 1 Input 2 Output
1
1
1
1
1
1
A logical inverter , sometimes called a NOT gate to differentiate it from other types of electronic
inverter devices, has only one input. It reverses the logic state.
Inverter or NOT gate
Input Output
1
1
The NAND gate operates as an AND gate followed by a NOT gate. It acts in the manner of the
logical operation "and" followed by negation. The output is "false" if both inputs are "true."
Otherwise, the output is "true."
NAND gate
Input 1 Input 2 Output
1
1
1
1
1
1
1
The NOR gate is a combination OR gate followed by an inverter. Its output is "true" if both
inputs are "false." Otherwise, the output is "false."
NOR gate
Input 1 Input 2 Output
1
1
1
1
1
The XNOR (exclusive-NOR) gate is a combination XOR gate followed by an inverter. Its output
is "true" if the inputs are the same, and"false" if the inputs are different.
XNOR gate
Input 1 Input 2 Output
1
1
1
1
1
1
Using combinations of logic gates, complex operations can be performed. In theory, there is no
limit to the number of gates that can be arrayed together in a single device. But in practice, there
is a limit to the number of gates that can be packed into a given physical space. Arrays of logic
gates are found in digital integrated circuits (ICs). As IC technology advances, the required
physical volume for each individual logic gate decreases and digital devices of the same or
smaller size become capable of performing ever-more-complicated operations at ever-increasing
speeds.
HALF ADDER CIRCUITS :With the help of half adder, we can design circuits that are capable of performing simple addition
with the help of logic gates.
Let us first take a look at the addition of single bits.
0+0 = 0
0+1 = 1
1+0 = 1
1+1 = 10
These are the least possible single-bit combinations. But the result for 1+1 is 10. Though this
problem can be solved with the help of an EXOR Gate, if you do care about the output, the sum
result must be re-written as a 2-bit output.
Thus the above equations can be written as
0+0 = 00
0+1 = 01
1+0 = 01
1+1 = 10
Here the output ‘1’of ‘10’ becomes the carry-out. The result is shown in a truth-table below.
‘SUM’ is the normal output and ‘CARRY’ is the carry-out.
INPUTS
OUTPUTS
A
B
SUM
CARRY
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
From the equation it is clear that this 1-bit adder can be easily implemented with the help of
EXOR Gate for the output ‘SUM’ and an AND Gate for the carry. Take a look at the
implementation below.
Half Adder Circuit
For complex addition, there may be cases when you have to add two 8-bit bytes together. This
can be done only with the help of full-adder logic.
FULL ADDER CIRCUITS :This type of adder is a little more difficult to implement than a half-adder. The main difference
between a half-adder and a full-adder is that the full-adder has three inputs and two outputs. The
first two inputs are A and B and the third input is an input carry designated as CIN. When a full
adder logic is designed we will be able to string eight of them together to create a byte-wide
adder and cascade the carry bit from one adder to the next.
The output carry is designated as COUT and the normal output is designated as S. Take a look at
the truth-table.
INPUTS
OUTPUTS
A
B
CIN
COUT
S
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
From the above truth-table, the full adder logic can be implemented. We can see that the output S
is an EXOR between the input A and the half-adder SUM output with B and CIN inputs. We
must also note that the COUT will only be true if any of the two inputs out of the three are
HIGH.
Thus, we can implement a full adder circuit with the help of two half adder circuits. The first will
half adder will be used to add A and B to produce a partial Sum. The second half adder logic can
be used to add CIN to the Sum produced by the first half adder to get the final S output. If any of
the half adder logic produces a carry, there will be an output carry. Thus, COUT will be an OR
function of the half-adder Carry outputs. Take a look at the implementation of the full adder
circuit shown below.
Full Adder Circuit
Though the implementation of larger logic diagrams is possible with the above full adder logic a
simpler symbol is mostly used to represent the operation. Given below is a simpler schematic
representation of a one-bit full adder.
Single-bit Full Adder
With this type of symbol, we can add two bits together taking a carry from the next lower order
of magnitude, and sending a carry to the next higher order of magnitude. In a computer, for a
multi-bit operation, each bit must be represented by a full adder and must be added
simultaneously. Thus, to add two 8-bit numbers, you will need 8 full adders which can be formed
by cascading two of the 4-bit blocks. The addition of two 4-bit numbers is shown below.
R-S FLIP FLOP :

A RS-flipflop is the simplest possible memory element. It is constructed by feeding the
outputs of two NOR gates back to the other NOR gates input.
The inputs R and S are referred to as the Reset and Set inputs, respectively.


To understand the operation of the RS-flipflop (or RS-latch) consider the following
scenarios:
o S=1 and R=0: The output of the bottom NOR gate is equal to zero, Q'=0.
o Hence both inputs to the top NOR gate are equal to one, thus, Q=1.
o Hence, the input combination S=1 and R=0 leads to the flipflop being set to Q=1.
o S=0 and R=1: Similar to the arguments above, the outputs become Q=0 and
Q'=1.
o We say that the flipflop is reset.
o S=0 and R=0: Assume the flipflop is set (Q=0 and Q'=1), then the output of the
top NOR gate remains at Q=1 and the bottom NOR gate stays at Q'=0.
o Similarly, when the flipflop is in a reset state (Q=1 and Q'=0), it will remain there
with this input combination.
o Therefore, with inputs S=0 and R=0, the flipflop remains in its state.
o S=1 and R=1: This input combination must be avoided.
We can summarize the operation of the RS-flipflop by the following truth table.
R S Q Q' Comment
0 0 Q Q' Hold state
0 1 1 0 Set
1 0 0 1 Reset
1 1 ? ? Avoid


Note, the output Q' is simply the inverse of Q.
An RS flipflop can also be constructed from NAND gates.
Figure 3.10: RS Flip-Flop composed of two NOR Gates.
J-K FLIP FLOP :This simple JK flip Flop is the most widely used of all the flip-flop designs and is considered to
be a universal flip-flop circuit. The sequential operation of the JK flip flop is exactly the same as
for the previous SR flip-flop with the same “Set” and “Reset” inputs. The difference this time is
that the “JK flip flop” has no invalid or forbidden input states of the SR Latch even when S and
R are both at logic “1”.
The JK flip flop is basically a gated SR Flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are equal
to logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input
combinations, “logic 1″, “logic 0″, “no change” and “toggle”. The symbol for a JK flip flop is
similar to that of an SR Bistable Latch as seen in the previous tutorial except for the addition of a
clock input.
The Basic JK Flip-flop
Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs
called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates to: J = S
and K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-input
NAND gates with the third input of each gate connected to the outputs at Q and Q. This cross
coupling of the SR flip-flop allows the previously invalid condition of S = “1” and R = “1” state
to be used to produce a “toggle action” as the two inputs are now interlocked.
If the circuit is now “SET” the J input is inhibited by the “0” status of Q through the lower
NAND gate. If the circuit is “RESET” the K input is inhibited by the “0” status of Q through the
upper NAND gate. As Q and Q are always different we can use them to control the input. When
both inputs J and K are equal to logic “1”, the JK flip flop toggles as shown in the following
truth table.
The Truth Table for the JK Function
Input
same as
for the
SR Latch
toggle
action
Output
J
K
Q
Q
0
0
0
0
0
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
0
Description
Memory
no change
Reset Q » 0
Set Q » 1
Toggle
Then the JK flip-flop is basically an SR flip flop with feedback which enables only one of its two
input terminals, either SET or RESET to be active at any one time thereby eliminating the
invalid condition seen previously in the SR flip flop circuit. Also when both the J and the K
inputs are at logic level “1” at the same time, and the clock input is pulsed either “HIGH”, the
circuit will “toggle” from its SET state to a RESET state, or visa-versa. This results in the JK flip
flop acting more like a T-type toggle flip-flop when both terminals are “HIGH”.
Although this circuit is an improvement on the clocked SR flip-flop it still suffers from timing
problems called “race” if the output Q changes state before the timing pulse of the clock input
has time to go “OFF”. To avoid this the timing pulse period ( T ) must be kept as short as
possible (high frequency). As this is sometimes not possible with modern TTL IC’s the much
improved Master-Slave JK Flip-flop was developed.
The master-slave flip-flop eliminates all the timing problems by using two SR flip-flops
connected together in a series configuration. One flip-flop acts as the “Master” circuit, which
triggers on the leading edge of the clock pulse while the other acts as the “Slave” circuit, which
triggers on the falling edge of the clock pulse. This results in the two sections, the master section
and the slave section being enabled during opposite half-cycles of the clock signal.