Question 1. 1. (TCO 3) A D-type flip-flop is triggered with a rising edge clock. If the flip-flop is set,
what condition will causes the flip-flop to reset? (Points : 7)
CLK = rising edge, D = 0
CLK = rising edge, D = 1
CLK = falling edge, D = 0
CLK = falling edge, D = 1
Question 2. 2. (TCO 3) What is the decimal equivalent of the largest number that can be stored in a 6bit binary counter? (Points : 7)
32
63
64
127
Question 3. 3. (TCO 3) If the inputs to a one-bit full-adder are A = 1, B = 0, Cin =1, what are the
outputs? (Points : 7)
Σ = 0, Cout = 0
Σ = 1, Cout = 0
Σ = 0, Cout = 1
Σ = 1, Cout = 1
Question 4. 4. (TCO 3) What is the minimum number of select lines required for an 8-to-1
demultiplexer? (Points : 7)
1
3
8
24
Question 5. 5. (TCO 3) What is the largest number that can be represented by 10 bits? (Points : 7)
512
1023
1024
2048
Question 6. 6. (TCO 3) A J-K flip-flop has Q = 1. The output will always change on the next clock edge
when (Points : 7)
J = 0, K = X.
J = X, K = 0.
J = X, K = 1.
J = 1, K = X.
Question 7. 7. (TCO 3) A production plant has a requirement for a counter that will count 4,000 items
before
recycling and starting over. How many flip-flops are required?
(Points : 7)
10
11
12
13
8=B
Question 9. 9. (TCO 3) If an input to a 3-input NAND gate is shorted to ground, the output is (Points :
7)
HIGH.
LOW.
switching.
unknown.
Question 10. 10. (TCO 3) How many flip-flops are required to create a MOD-25 counter? (Points : 7)
5
10
20
25
Question 11. 11. (TCO 3) In the decimal number 481, what is the powers-of-ten weight of the digit 4?
(Points : 7)
400
100
101
104
Question 12. 12. (TCO 3) How many entries are required in a truth table to describe all states for a 4input NAND gate? (Points : 7)
4
8
16
32
Question 13. 13. (TCO 3) A periodic signal is HIGH for a time ton and LOW for a time toff. The formula
for duty cycle is (Points : 7)
13=C
Question 14. 14. (TCO 3) Which flip-flop timing parameter defines the time required between data input
steady and a clock edge? (Points : 7)
Set-up time
Propagation delay
Hold time
Rise time
Question 15. 15. (TCO 3) A MOD-5 and a MOD-20 counter are cascaded. What is the output frequency
if the input frequency is 60 MHz? (Points : 7)
6 MHz
2.4 MHz
600 kHz
240 kHz
Question 16. 16. (TCO 3) What components are used as switches in TTL and CMOS logic? (Points :
7)
Capacitors
Diodes
Relays
Transistors
Question 17. 17. (TCO 3) Convert the truth table below to its equivalent Boolean equation.
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
0 (Points
: 7)
17 C
Question 18. 18. (TCO 3) How many logic states does a MOD-16 counter have? (Points : 7)
15
16
17
32
Question 19. 19. (TCO 3) Select the FPGA look-up table for a 1-to-2 demultiplexer with a data input D,
select line S, and outputs Y0 and Y1. (Points : 7)
19=A
Question 20. 20. (TCO 3) The VHDL signal assignment statement for a 3-input NOR gate is (Points :
7)
X <= not(A or B or C);.
X <= not A or not B or not C.
X <= not(A and B and C);.
X <= A nor B nor C;.
Question 21. 21. (TCO 3) What is the VHDL assignment operator? (Points : 7)
:=
<=
=>
=
22=B
Question 23. 23. (TCO 3) What is the duty cycle for the most-significant bit of the 3-bit counter whose
state diagram is the following?
(Points : 7)
10%
33.3%
66.7%
90%
Question 24. 24. (TCO 3) How many state variables are in a MOD-27 counter? (Points : 7)
27
5
26
4
Question 25. 25. (TCO 3) What creates an unconditional transition between states in a state machine?
(Points : 7)
Inputs only
Inputs and outputs
Inputs or outputs
Outputs only