PCI Express 3.0 by Wizlogix & MindShare
Course Objectives:
This course aims to update the Engineers’ knowledge of the third-generation, high performance InputOutput (I/O) bus which interconnects peripheral devices in computing and communications
platform. Engineers need to ensure that their technical know-how remains relevant as PCI Express has
been designed into consumer and high-end computers, embedded computing and communications
market, having become a popular platform (or bus) for the I/O connections. Even though the course is
hardware-oriented, it is also suitable for software engineers as the configuration registers used to
control the hardware are covered in detail. The course is ideal for Register-Transfer Level (RTL-), chip-,
system- or system board-level design engineers who need a broad understanding of PCI Express.
Because the course contains practical examples of transactions on the various bus interfaces, the course
is also suitable for chip-level and board-level validation engineers.
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Background Foundation
PCI Express Overview
Transaction Characteristics
Address Space and Transaction Routing
Flow Control
Transaction Ordering
ACK/NAK Protocol
Physical Layer Logic
Error Detection and Handling
System Resets
Link Initialization & Link Training
Physical Layer Electrical
Power Management Overview
Interrupt Support
Configuration Registers
Changes for PCIe 3.0 backward compatibility
Higher Speed operation and link training
Optimized buffer flush/fill
Course Outline:
This five-day PCI Express System Architecture course will help you gain a deep understanding of PCI
Express, how it works, what it can do and why it’s the bus of choice for on-board I/O connections.
Starting with a high-level view of the design, the course then drills down to the fundamentals of each
part of the design. By course completion, you will have taken a direct route to a thorough understanding
of both hardware and software protocols.
Who Should Attend:
This course is hardware-oriented but is suitable for hardware, software or firmware engineers because
the configuration registers used to control the hardware are covered in detail. It is ideal for RTL-, chip-,
system or system board-level design engineers who need a broad understanding of PCI Express. It also
contains practical examples of transactions on the various bus interfaces, the course is also suitable for
chip-level and board-level validation engineers.
Date of Programme: 15 – 19 July 2013
Time: 9:00am – 5:00pm
Venue: To be advised
Course Fees:
SGD 3,999/person for 30 person
Up to 50% Training Grant*: SGD 1,999.50/person (excluding GST)
* Training Grants are only available for Singaporean & PR that are employed by a Singapore based
company (subject to approval)
How to Register:
Please contact us at resources@wizlogix.com