EXPERIMENT 5: FLIP-FLOPS AND FEEDBACK DEVICES
PURPOSE
In this experiment we shall explore the behavior of various types of latches and flip-flops. The
objective is to become familiar with flip-flop (FF) concepts and operational characteristics and to
become familiar with the design and implementation of sequential circuits..
INTRODUCTION
The combinational logic networks considered in the previous experiments do not have the
capability of storing information, i.e., their present outputs depend only on their present inputs.
However, logic which provides control for other circuits produces outputs that depend upon past
inputs, as well as present inputs; hence, virtually all digital logic systems performing significant
tasks must incorporate elements for storing information. A variety of techniques for information
storage are available. Most of them entail storing information in bits and are characterized by
the speed at which information can be stored and retrieved. Our consideration will be restricted
to only integrated circuit devices and flip-flops.
LATCH
The most primitive memory element is the latch. An RS NAND latch consists of a crosscoupled pair of NAND gates as shown in Figure 5.1(b). The operation of this latch is illustrated
in Figure 5.1(a). The arrows indicate cause and effect relationships. The tail of the arrow
represents the cause and the head represents the effect. When the SET input goes LOW, the
output Q goes HIGH. When the RESET input goes LOW, the output Q goes LOW. When both
SET and RESET are HIGH, the output remains unchanged. Under normal operation, the output
Q' is the complement of output Q. Hence, a latch acts as a memory element by retaining
information indicating the last input to go LOW.
If SET and RESET are both LOW, both outputs Q and Q' will be HIGH. If now both inputs go
HIGH simultaneously, the state of the latch is indeterminate. The new value of Q is
unpredictable. Thus, the SET and RESET inputs are usually prohibited from being LOW
simultaneously. (Note: With this notation for the latch, SET and RESET cause their actions
when they are low. Alternatively, the inputs to the latch can be labeled SET’ and RESET’, then
the signals SET and RESET cause their actions when high.)
5.1
Figure 5.1 RS NAND Latch.
A simple application of the RS NAND latch is illustrated in Figure 5.2. By connecting the latch,
as shown, to a switch, a contact bounce free signal is provided. This circuit an output that
changes only once no matter how many times the switch make and break contact as it bounces.
The circuit is based on the assumption that TTL floating inputs act as if they were provided with
HIGH inputs. The momentary breaks in contact of the switch pole with a switch terminal while
the contacts are bouncing (after the switch make initial contact) provides the circuit with floating
inputs. However, since the latch remains unchanged when both inputs are HIGH, the output is
unaffected by contact bounce. The circuit should be made more reliable by connecting pullup
resistors to both contacts of the switch to assure that an input is a logic 1 when the switch is not
connected to it.
Figure 5.2 Switch Debounce Circuit.
From Figure 5.2, it is clear that the latch output immediately follows changes in the inputs after
one or two gate propagation delays. In this configuration, it is not possible to control the
5.2
moment at which the output changes as a result of an input change. The input change alone
triggers the subsequent output change. Circuits constructed from such unclocked devices as
latches are referred to as asynchronous circuits. The design of asynchronous circuits is much
more involved than that of synchronous circuits, in which changes of the memory element
outputs are synchronized by a clock. Sequential circuit design is greatly simplified through the
use of clocked flip-flop (FF) memory elements. Virtually all complex sequential systems use
them. In synchronous circuits, the length of the clock period can be controlled so that when the
outputs of FFs change, these changes are allowed to propagate through the combinational logic
and provide stable inputs to the FFs before the next clock pulse enables the FFs to change again.
Hence, any glitches in the outputs of combinational logic that may occur are not important in
synchronous circuits.
GATED LATCHES
The gated NAND RS latch memory element is illustrated in Figure 5.3(b). (This circuit is also
called a transparent latch or a latch with enable.) Its operation can be synchronized with a clock
signal by connecting the enable to a clock, but by itself, it is not a clocked FF, i.e., it does not
avoid many of the problems mentioned above.
Figure 5.3 Gated RS Latch Controlled by a Clock Signal.
5.3
From the timing diagram in Figure 5.3(a), it is seen that the outputs cannot change while the
clock is LOW. The circuit acts essentially as a latch when the clock is HIGH. Hence, any
changes on the inputs while the clock is HIGH will propagate to the outputs. The clock input
controls the times at which the outputs may change in accordance with the R and S inputs. In
this sense, its operation is synchronized to the clock. However, if we were to design a system
using these gated latches all controlled by the same clock, there are severe timing problems.
Once the gated RS Latch is enabled by the clock going high, its outputs can change according to
the present inputs. If the clock input is not disabled before the resulting output changes
propagate through the circuit and back to the original latch inputs or to another latch controlled
by the same clock, the latch outputs can change again. For predictable operation, each latch
should change only once for each application of the clock. Hence, clock pulses should be long
enough to enable the FF's outputs to change and yet short enough so that no output changes are
permitted to propagate to latch inputs while the clock is still HIGH. Unfortunately, this is
difficult to guarantee.
The preceding problem can be avoided by using gated latches controlled by two-phase clock
signals. In a circuit using these, the outputs from latches controlled by one phase of the clock are
only allowed to propagate to latches controlled by the other phase of the clock. Hence, the
inputs to a latch will not change while it is enabled. Master-Slave flip-flops are a variation of the
two-phase clock approach.
MASTER-SLAVE JK FLIP-FLOPS
The master-slave JK flip-flop is better suited for synchronizing input changes in order to
eliminate the difficulties discussed in the previous section. The master-slave JK FF is illustrated
in Figure 5.4. It consists of two gated RS NAND FF's in tandem, one of which is enabled by the
clock while the other is enabled by the complement of the clock. In addition, two paths feed
back from the outputs to the inputs in order to generate the JK behavior.
5.4
Figure 5.4 Master-slave JK FF.
While the clock is LOW, the master is unaffected by any input changes. Hence, its outputs
remain stable. On the other hand, the slave is enabled, and changes its state according to the
master's outputs. Any output changes propagating through the circuit back to the FF inputs of
the master cannot affect the FF since the master is disabled. When the clock is HIGH, the slave
is disabled and the master enabled. Thus, the outputs from the slave remain stable, and hence,
the inputs feed back to the master remain stable.
Note that while the clock is HIGH, the master functions as an enabled latch. Any momentary
pulses appearing at the FF's inputs may alter its state. For example, for the slave FF output Q=0,
a momentary pulse on the master's J input, while the clock is HIGH, can SET the master which
was previously RESET. There is no way to reset the master until the next clock pulse. When the
clock returns LOW, the slave will subsequently be SET. For this reason, the master-slave JK
flip-flop is referred to as "1's catching". No false pulses should occur on J or K while the clock
is HIGH. Thus, the propagation of all signals through the logic must be completed while the
clock is LOW. Also, in order to minimize the risk of corruption of circuit operation by noise, it
is advisable to make the clock pulse widths as short as possible, minimizing the time the master
is enabled. These requirements lead to the use of asymmetrical clock signals and limit the
operational speed of the circuit.
Figure 5.4 shows two additional inputs besides J, K, and the clock. The preset (PR) and clear
(CLR) are asynchronous inputs which immediately set and reset the FF, respectively, regardless
of the other inputs.
EDGE TRIGGERED FLIP-FLOPS
Edge triggered flip-flops have the advantage of being sensitive to their inputs only for a short
time around the rising or falling clock pulse edge, rather than throughout the entire clock pulse,
5.5
as with the master-slave flip-flops. For example, the signals propagating through combinational
logic to the inputs of a negative edge-triggered flip-flop need not be stabilized before the next
leading positive edge of the pulse, in contrast to the case for the other types of flip-flops we have
considered. Thus, a shorter clock period can be used, and, hence, faster operation is possible. In
addition, the clock pulses need not be asymmetric, as with the previous flip-flops. The period
during which the clock is LOW can be the same as that during which it is HIGH, without
lowering the pulse frequency. This reduces the amount of circuitry required to generate the clock
pulses. Since the operation of an edge-triggered flip-flop is quite complex, it will not be
considered here: Refer to the discussion in your text.
Figure 5.5 illustrates the operation of both a positive and negative edge triggered JK flip-flop.
Figure 5.5 Positive and Negative Edge-triggered Flip-flop Behavior.
Two parameters which are significant to edge-triggered flip-flop operation will be presented.
Suppose we assume a negative edge triggered flip-flop. Figure 5.6 illustrates the conditions for
the J and K signals for correct operation. The cross hatched areas indicate when it is permissible
for J and K to change.
5.6
Figure 5.6 Setup and Hold Times.
The time interval for which J and K must be stable at their correct values prior to the active clock
transition is the setup time, tsetup. The time interval for which J and K must be held stable at
their correct values following the active clock transition is the hold time, thold. It turns out that
in some logic families, the signals on the J and K inputs may change before the active clock
edge. In this case, the time before the active clock edge at which J and K may change is referred
to as the release time, trelease. These parameters determine the maximum clock period and/or
maximum number of combinational logic levels between flip-flop inputs and outputs. The
parameters for positive edge triggered flip-flops are found similarly.
The symbols for JK flip-flops are illustrated in Figure 5.7. Note that the symbols do not
distinguish the master-slave from the negative edge-triggered flip-flop. This information must
be ascertained from the flip-flop's part number and data sheet. The small triangle is used to
designate the clock terminal. A small circle at the clock terminal indicates that the flip-flop
changes state on a negative-going signal, while the absence of the circle indicates that the state
changes on a positive-going signal. Each flip-flop shown has a preset (PR) and clear (CLR)
terminal. If PR is set LOW, while CLR is HIGH, the flip-flop is set immediately
(asynchronously). If CLR is LOW, and PR is HIGH, the flip-flop is reset immediately. Setting
both CLR and PR LOW is forbidden. The small circles on the PR and CLR inputs indicate
active LOW signals on these terminals.
Figure 5.7 Flip-flop Symbols.
5.7
The behavior of all three flip-flops is shown in Figure 5.8 assuming J and K are held fixed
throughout the appropriate setup and hold times. The first column under CLK pertains to
master-slave/negative edge-triggered FF's. The second column pertains to positive edgetriggered FF's. X indicates that the input has no effect. Z0 represents the flip-flop state prior to
the activating signal, and Z1 represents the state after the activating signal.
Figure 5.8 Behavior of JK Flip-flops.
5.8
PRELAB
1.
Suppose a gated RS NAND latch were used as a clocked RS NAND FF, i.e., a clock
signal is connected to the gate input. Should the R and S signals be allowed to change while the
clock is HIGH? Why or why not? Can you define a setup and hold time for this flip-flop as was
defined for edge-triggered flip-flops? How does the clock (gate) determine these times? Should
the clock pulses be HIGH for the same duration they are low? Why or why not? If not, how
long should clock pulses remain HIGH? Construct such an RS latch with enable. Use two logic
level switches to provide the S and R inputs and a third to provide the Enable input. The outputs
may be observed on the LED's. Hand in your design.
2.
The master-slave JK FF is said to be "1's catching". Explain the reason for this term and
how "1's catching" can occur.
3.
Design a circuit realizing the transition table shown below.
a). Draw a transition diagram from the table.
b). Assuming the D-type flip-flops are given, use the transition table to find the K-map and
obtain a minimal sum-of-products form for each flip-flop input.
c). Draw out a schematic diagram for the state machine using three 74LS74 D-type flip-flops.
Remember that when the circuit is powered-up, it needs to start in a particular state, i.e., the
power-up state of the circuit cannot be random. Select an initial state that seems reasonable for
this circuit.
PRESENT STATE
A
B
C
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
NEXT STATE
NA NB NC
1
0
0
1
0
0
0
0
1
1
0
1
1
1
0
0
1
0
0
1
1
1
1
1
5.9
PROCEDURE
Before performing the procedures listed below, read the report section of the experiment to
assure you make all required measurements and record all required data.
A. RS Latch with Enable
1. Connect the R, S, and enable inputs of the gated RS NAND latch, which you
constructed in the prelab, to the toggle switches on the logic box. Observe the outputs on two of
the logicbox LED's for the following input sequence:
2. With the enable input HIGH, observe the outputs on the oscilloscope for the
following input sequence obtained by using a single toggle switch to supply the same signal to
both R and S:
Does the latch always have the same output values after S and R return LOW? If so, would the
outputs be the same if the S and R inputs were interchanged and the Q and Q' outputs were
interchanged, i.e., if the positions of the gates were interchanged in the circuit.
5.10
B. Master-Slave Flip-Flop
1. Complete the following table using the logic box toggle switches to provide the J, K
and Clock inputs to a 7476 J-K master-slave flip-flop (Note: be sure to use the 7476 FF and not
the 74LS76 FF) and two logic box LED's to display the outputs:
JK
00
00
01
01
10
10
11
11
Q
Before  edge CLK
0
1
0
1
0
1
0
1
Q
While CLK = 1
Q
After _ edge CLK
2. Complete the output waveform for the following J, K, and clock inputs provided by
the toggle switches on the logic box. Note that, in violation of the usual assumptions for masterslave flip-flops, the J and K inputs change while the clock is HIGH.
3. This FF also has PRESET and CLEAR inputs available for asynchronous operation.
In order to determine their effects, apply signals to these inputs, similar to those applied to the
gated RS NAND latch, except inverted (inverted signals of S and R in A.1 and A.2). Verify that
signals on these terminals override the effects of all signals applied to J, K, and the clock.
5.11
C. J-K Edge Triggered Flip-Flops
1. Repeat step 1 in part B for a 74LS76 J-K Negative-Edge Triggered Flip-Flop. Compare
the results to that obtained in part B.
2. Repeat step 2 of part B for the 74LS76 FF and compare the results with that obtained
in part B.
5.12
EXPERIMENT 5--FLIP-FLOPS AND FEEDBACK DEVICES
FINAL REPORT
I. RS Latch with Enable
a). Plot the response of the gated RS NAND latch you observed for the following input
sequence in part A.1:
Q
Q'
b). Plot the response of the latch observed in part A.2 for the following input sequence:
Q
Q'
c). Does the latch always have the same output value on Q after both S and R return to 0
at the same time? If so, might this change if the upper and lower gates were swapped in the
circuit? Explain. Give two reasons why this latch should not be used with both inputs
simultaneously 1.
5.13
II. Master-Slave Flip-Flop
a). Fill in the following table based on your observations of the operation of the 7476 JK
master-slave FF in the lab. On the basis of this table, which input sets the device, which input
resets the device, and which part of the clock pulse effects changes in the state (output) of the
flip-flop.
JK
00
00
01
01
10
10
11
11
Q
Before  edge CLK
0
1
0
1
0
1
0
1
Q
While CLK = 1
Q
After _ edge CLK
b). Plot the waveforms observed for the JK master-slave flip-flop in part B.2. Do the
changes on the J and K inputs, while the clock is high, affect the output?
5.14
c). Based upon your observations in part B.3, what are the effects of the PRESET and
CLEAR lines on the 7476 FF? How are these changes affected by pulses on the J, K, and CK
lines?
III. J-K Edge-Triggered Flip-Flops
a). Using your lab results, fill in the following table for the 74LS76 negative edgetriggered FF. How does this table compare with the corresponding table for the JK master-slave
FF?
JK
00
00
01
01
10
10
11
11
Q
Before ↑ edge CLK
0
1
0
1
0
1
0
1
Q
While CLK = 1
Q
After ↓ edge CLK
5.15
b). Show the waveforms observed for the 74LS76 flip-flop in part D.2 of the experiment.
Compare this to the corresponding graph for the JK master-slave FF.
IV. Conclusion
Write a brief description of the operation of the various latches and flip-flops based on your
laboratory observations. Compare the performance of the basic latch, the master-slave flip-flop,
and the edge-triggered flip-flop. What are the advantages and disadvantages of each design?
For what applications are each best suited?
5.16