11.2 Discussion ................................................................................
11.2.0 The 555 Timer ...........................................................
11.2.1 Opto-Isolators ...........................................................
11.2.2 DIP Relays .................................................................
11.2.3 Programmable Logic Devices ...............................
11.3 Summary ...............................................................................
11.4 Review Questions ...............................................................
Lab Exercise 11.1 The 555 Timer ................................................
Lab Exercise 11.2 DIP Relays ......................................................
Lab Exercise 11.3 The Opto-Isolator ..........................................
Lab Exercise 11.4 Implementing Logic Functions
with ROMS ............................................................................
CHAPTER 12
APPENDIX
1
226
226
227
227
228
231
231
232
234
236
238
Microcomputer Concepts ..............................................................
12.0 Introduction ..........................................................................
12.1 Objectives ..............................................................................
12.2 What is a Microcomputer? ................................................
12.2.0 Organization of the Microcomputer ...............
12.2.1 Interfacing .............................................................
12.2.1.0 Parallel and Serial Data Transmission
12.2.2 Programming ......................................................................
12.2.2.0 Machine Code .......................................
12.2.2.1 Assembly Language ............................
12.2.2.2 High Level Language ..........................
12.3 Summary ...........................................................................
12.4 Review Questions ...............................................................
241
241
241
242
243
247
249
251
252
254
255
257
257
Pinouts of ICs Used in the LK-1 Kit ............................................
259
FIGURE 1-1.
FIGURE 1-2.
FIGURE 1-3.
Typical Analog Signals .................................... 2
Typical Digital Signals or Words ................... 4
Comparison of Binary and Decimal
Numbers .............................................................. 6
FIGURE 1-4.
Schematic Diagram of a Digital Switch ......... 6
FIGURE 1-5.
BJT (Bipolar Junction Transistor)
Inverter ................................................................ 7
FIGURE 2-1.
Structure of a General Positional
Number System .................................................. 12
FIGURE 2-2.
Converting 214 Decimal to Binary ................. 15
FIGURE 2-3.
Binary to Hexadecimal Number
System Conversion .......................................... 16
FIGURE 2-4.
Binary/Octal Number System
Conversions ...................................................... 16
FIGURE 2-5.
Decimal Number Coded in BCD ................... 17
FIGURE 3-1.
Truth Tables ........................................................ 23
FIGURE 3-2.
Truth Table for the OR Operation ................. 24
FIGURE 3-3.
Logical AND Truth Table ................................. 24
FIGURE 3-4.
Truth Table for the NOT Operation .............. 25
FIGURE 3-5.
Schematic Symbols for Boolean
Equations ............................................................ 27
FIGURE 3-6.
Designing Circuit from Logic Equations ...... 27
FIGURE 3-7.
Schematic Symbols for NAND and
NOR Gates .......................................................... 28
FIGURE 3-8.
IC Orientation and Pin Numbering ............. 31
FIGURE 3-9.
Basing Diagram for 74LS04 IC........................ 32
FIGURE 3-10A. HIGH Pulse Circuit .............................................. 32
FIGURE 3-10B. LOW Pulse Circuit ................................................ 32
FIGURE 3-11. Circuit Schematic ................................................ 38
FIGURE 3-12. Circuit Schematic ................................................ 39
FIGURE 4-1.
Circuit Implementation of Minterm
Expression .......................................................... 44
FIGURE 4-2.
A Simplified Alarm Logic Circuit ................. 45
FIGURE 4-3.
DeMorgan's Theorem ....................................... 45
FIGURE 4-4.
Logic Expressions, Truth Tables and
K-Maps for Two, Three and Four Input
Variables ............................................................. 46
FIGURE 4-5.
Examples of Looping ........................... t................... 48
FIGURE 4-6.
K-Map Simplification Examples .................... 49
FIGURE 4-7.
K-Map Applied to Ink Factory
Alarm Problem ................................................... 50
FIGURE 4-8.
Don't Care Conditions in K-Map
Simplification .................................................... 50
ILLUSTRATIONS
FIGURE 4-9.
Examples of Product-of-Sums Logic
Equation ................................................................
FIGURE 4-10. Steps in Creating the Product-of-Sums
Logic Equation .....................................................
FIGURE 4-11. Implementation of the Equations in
Figure 4-10 ............................................................
FIGURE 4-12. Logic Implementation Using
Universal Gates ..................................................
FIGURE 4-13. The Exclusive OR Gate and Exclusive
NOR Gate ..............................................................
FIGURE 4-14. K-Maps .....................................................................
FIGURE 4-15. Outputs for XOR and XNOR Gates .....................
FIGURE 4-16. Examples of Minterm Truth Tables ....................
FIGURE 4-17. Examples of Maxterm Truth Tables ...................
FIGURE 4-18. Truth Table for Lab Exercise 4.2 ...........................
FIGURE 4-19. Step 7 Circuit Schematic .......................................
FIGURE 4-20. Two Variable Karnaugh Map ..............................
FIGURE 4-21. Schematic of a Simple Decoder ...........................
FIGURE 4-22. Schematic for a One of Four Decoder ................
FIGURE 4-23. Schematic for a Simple Encoder ...........................
FIGURE 4-24. EXOR Truth Table...................................................
FIGURE 4-25. EXOR Schematic #1 ...............................................
FIGURE 4-26. EXOR Schematic #2.................................................
FIGURE 4-27. The EXNOR Circuit ..............................................
FIGURE 5-1. OR Gate Latch .......................................................
FIGURE 5-2. NOR Gate Latch ....................................................
FIGURE 5-3. NOR "S-C" Flip-flop ...........................................
FIGURE 5-4. Basic NAND Latch ...............................................
FIGURE 5-5. NAND "S-C" Latch .............................................
FIGURE 5-6. NOR "D" Latch ......................................................
FIGURE 5-7. NAND "D" Latch ................................................
FIGURE 5-8. Clocked "S-C" Flip-flop ........................................
FIGURE 5-9
Clocked "T" Flip-flop ...........................................
FIGURE 5-10. Timing Diagram for "T" Flip-flop .......................
FIGURE 5-11. Clocked "D" Flip-flop ............................................
FIGURE 5-12. "J-K" Flip-flop .........................................................
FIGURE 5-13. "J-K" Hip-flop Configurations .............................
FIGURE 5-14. "J-K" Master-slave Flip-flop Circuit
Diagram .................................................................
FIGURE 5-15. Schematic Symbol for Edge Triggered
Flip-flop .................................................................
51
52
53
53
55
55
57
58
59
62
63
63
66
66
68
70
70
71
73
76
77
77
78
79
79
80
81
82
82
83
84
85
85
90
FIGURE 5-16. Edge Trigger Circuits.............................................. 91
FIGURE 5-17. Schematic for NOR "S-C" Flip-flop ..................... 91
FIGURE 5-18. Schematic for NAND "S-C" Flip-flop ................. 92
FIGURE 5-19. Schematic for "D" Flip-flop .................................. 93
FIGURE 5-20. Schematic for Clocked "S-C" Flip-flop ................ 96
FIGURE 5-21. Schematic for "T" Flip-flop ................................... 97
FIGURE 5-22. Schematic for Clocked "D" Flip-flop ................... 99
FIGURE 5-23. "J-K" Flip-flop Schematic ...................................... 100
FIGURE 5-24. Schematic for Step Seven ...................................... 101
FIGURE 5-25. "One-Shot" Schematic ............................................. 102
FIGURE 6-1. Rules of Binary Addition ................................... 106
FIGURE 6-2. Example of Signed Numbers ............................. 106
FIGURE 6-3. Rules for Binary Subtraction ................................ 107
FIGURE 6-4. Examples of Complement Notation ................. 107
FIGURE 6-5. Subtraction Using Two's Complement
Notation ................................................................. 108
FIGURE 6-6. Example of Multi-Digit Binary
Multiplication ....................................................... 109
FIGURE 6-7. Alternate Method for Multiplying Binary
Numbers .............................................................. 109
FIGURE 6-8. Alternate Method for Division .......................... 110
FIGURE 6-9. Binary Division by the Restoring Method ....... Ill
FIGURE 6-10. BCD Addition Examples ........................................ Ill
FIGURE 6-11. Half-Adder ............................................................... 112
FIGURE 6-12. Full-Adder ................................................................ 113
FIGURE 6-13. Parallel Adder IC..................................................... 114
FIGURE 6-14. BCD Adder Circuit.................................................. 114
FIGURE 6-15. Half-Adder Schematic ............................................ 117
FIGURE 6-16. Full-Adder Schematic ........................................... 118
FIGURE 6-17. Parallel Binary Adder Circuit .............................. 119
FIGURE 6-18A. BCD Adder Circuit ................................................ 122
FIGURE 6-18B. Display Circuit ........................................................ 122
FIGURE 6-19. 74181 Adder ............................................................. 124
FIGURE 7-1. Examples of Ripple Counters ............................ 128
FIGURE 7-2. Count Rate Formula ........................................... 129
FIGURE 7-3. Clock and Strobe Pulses ....................................... 129
FIGURE 7-4. Examples of Down Counters ............................. 130
FIGURE 7-5. Parallel Counter Circuit ..................................... 131
FIGURE 7-6. Parallel Up/Down Counter ................................ 132
FIGURE 7-7. Presetable Counter ................................................ 133
FIGURE 7-8. "J-K" Flip-flop Shift Register .............................. 134
FIGURE 7-9. "D" Rip-flop Shift Register ................................. 135
FIGURE 7-10. Johnson Counter ................................................... 136
FIGURE 7-11. 74174 Logic Diagram ............................................... 137
FIGURE 7-12. 74174 PIPO Shift Register ...................................... 138
FIGURE 7-13. 7494 Logic Diagram ................................................. 139
FIGURE 7-14. 74165 Logic Diagram .............................................. 139
FIGURE 7-15. 74164 Logic Diagram ............................................... 140
FIGURE 7-16. Up Counter .............................................................. 143
FIGURE 7-17. Synchronous Up Counter .................................... 145
FIGURE 7-18A. Decade Counter ...................................................... 147
FIGURE 7-18B. Seven Segment Display .......................................... 147
FIGURE 7-19. 4-Bit Binary Up/Down Counter ........................... 148
FIGURE 7-20. SISO Shift Register.................................................. 150
FIGURE 7-21. 74174 PIPO Shift Register ...................................... 151
FIGURE 7-22. 74165 PISO Shift Register ....................................... 153
FIGURE 7-23. 74164 SIPO Shift Register ..................................... 154
FIGURE 8-1. Typical Pulse Signal ........................................... 158
FIGURE 8-2. Diode Logic Gates ................................................. 160
FIGURE 8-3. Basic TTL Circuit .................................................. 160
FIGURE 8-4. Sinking and Sourcing Current .......................... 161
FIGURE 8-5. Simple Inverting Amplifier Output ................. 164
FIGURE 8-6. Totem-Pole Output Amplifier .......................... 165
FIGURE 8-7. Open Collector TTL Gate .................................... 166
FIGURE 8-8. Examples of Wired Logic .................................. 166
FIGURE 8-9. Three-State Logic ................................................ 168
FIGURE 8-10. Schottky Barrier Diode Circuits ....................... 169
FIGURE 8-11. MOSFET Construction ......................................... 170
FIGURE 8-12. Methods of Interfacing TTL and CMOS ............ 172
FIGURE 8-13. CMOS/TTL Interfacing ........................................ 180
FIGURE 8-14. TTL/CMOS Interfacing ........................................ 180
FIGURE 9-1. BCD to Decimal Decoder Logic Diagram ....... 182
FIGURE 9-2. Seven-Segment Display Labeling ..................... 183
FIGURE 9-3. Logic Diagram BCD to Seven Segment
Decoder-Driver IC ............................................... 184
FIGURE 9-4. Decimal to BCD Encoder ................................... 186
FIGURE 9-5. 8-Line to 3-Line Priority Encoder ..................... 187
FIGURE 9-6. Simple Multiplexer Logic Diagram ................. 188
FIGURE 9-7. Parallel to Serial Conversion Using a
Multiplexer ........................................................... 188
FIGURE 9-8. 8-Input MUX Logic Diagram ............................ 189
FIGURE 9-9. Multiplexer Used as a Boolean Function
Generator ............................................................... 190
FIGURE 9-10. Simple Demultiplexer ........................................... 191
FIGURE 9-11. Serial to Parallel Conversion Using
a Demultiplexer .................................................. 192
FIGURE 9-12. BCD/DEC Decoder .................................................. 196
FIGURE 9-13. BCD/7-Segment Decoder ...................................... 198
FIGURE 9-14. 8-Line to 3-Line Encoder ....................................... 200
FIGURE 9-15. Simple Multiplexer ................................................ 202
FIGURE 9-16. Simple Demultiplexer ........................................... 203
FIGURE 10-1. Basic D/A Converter Block Diagram ................. 206
FIGURE 10-2. Simple D/A Converter ......................................... 207
FIGURE 10-3. Binary Ladder D/A Converter ............................ 208
FIGURE 10-4. Ladder Analysis for A4 .......................................... 209
FIGURE 10-5. Flash A/D Converter ............................................ 211
FIGURE 10-6. Successive Approximation A/D
Converter ............................................................. 212
FIGURE 10-7. Sample and Hold Circuit ........................................ 213
FIGURE 10-8. Rotary Switch ......................................................... 214
FIGURE 10-9. Typical Data Acquisition Systems ...................... 215
FIGURE 10-10. Simple D/A Converter ....................................... 218
FIGURE 10-11. A/D Converter ..................................................... 220
FIGURE 10-12. MUX Circuitry ....................................................... 222
FIGURE 11-1. 555IC Basing and Circuit Diagrams .................... 226
FIGURE 11-2. PAL Architecture ................................................... 228
FIGURE 11-3. ROM Architecture ................................................. 229
FIGURE 11-4. PCA Architecture .................................................... 230
FIGURE 11-5. One-Shot Circuit .................................................... 232
FIGURE 11-6. Astable Circuit ......................................................... 233
FIGURE 11-7. DIP Relay .................................................................. 234
FIGURE 11-8. Opto-Isolator TTL/CMOS Converter .................... 236
FIGURE 11-9. Programming Circuit ............................................ 238
FIGURE 12-1. Computer Families ................................................ 242
FIGURE 12-2. Generalized Microcomputer ................................ 244
FIGURE 12-3. Parallel Port Functional Diagram ........................ 249
FIGURE 12-4. Serial Port Functional Diagram ........................... 250
FIGURE 12-5. Industry Standard Data Bus Definitions ............ 251
TABLES
TABLE 2-1.
TABLE 2-2.
TABLE 2-3.
TABLE 2-4.
TABLE 2-5.
TABLE 3-1.
TABLE 4-1.
TABLE 4-2.
TABLE 8-1.
TABLE 8-2.
TABLE 8-3.
TABLE 9-1.
TABLE 11-1.
Structure of the Binary Number System .......
Converting 11010110 Binary to Decimal 214
Additional Digits for the Hexadecimal
System..................................................... • ...........
Excess-3 BCD Code.............................................
ASCII Code ..........................................................
Basic Laws of Boolean Algebra .........................
Truth Table and Minterm Expression ............
Boolean Theorems .............................................
TTL Characteristics .............................................
Typical TTL Parameters .....................................
CMOS Logic Characteristics .............................
Boolean Products of an 8-Bit Multiplexer .....
Data Table..............................................................
14
14
15
17
18
26
43
44
161
164
171
190
239
WARNING
FEDERAL REGULATION (PART 15 OF FCC RULES)
PROHIBITS THE USE OF COMPUTING EQUIPMENT
WHICH CREATES RADIO OR TV INTERFERENCE
Global Specialties LLC specifically warns the user of this instrument that it is intended for use in a classroom or laboratory
environment for the purpose of learning and experimentation. When building experimental circuits, it may emit interference that
will effect radio and television reception and the user may be required to stop operation until the interference problem is
corrected. Home use of this equipment is discouraged since the likelihood of interference is increased by the close proximity of
neighbors.
CORRECTIVE MEASURES:
Interference can be reduced by the following practices.
1) Install a commercially built RFI power filter in the power line at the point where the cord enters the unit.
2) Avoid long wires. They act as antennas.
3)
If long wires must be used, use shielded cables or twisted pairs which are properly grounded and terminated.
8
9