1. Submit the layout for the "exploded inverter" as discussed in Section 3.9. Make sure that you label
all the layers.
Figure 1 shows the various layers of the exploded inverter view. The following is an explanation of what
each layer does.
Figure 1 Exploded view of the inverter showing all layers
2. With reference to the TSMC layers as defined in the process documentation, explain what each
"Cadence layer" corresponds to in terms of the TSMC masks. Explain how the masks are created based
on the layers drawn in Cadence.
Note: All layers are drawing (dg) layers, unless otherwise indicated.
Also note: Information about the masks was taken from the CMOSP35 design rules (page 10 on the
pdf file)
prBound : Boundaries for use for the place & route tool. After a design is synthesized (ie. an HDL
description is turned into a netlist of consisting of a set of interconnected standard cells), a tool
attempts to instantiate the design by implementing the various required cells and adding interconnect
between them. In order to place the cells appropriately, the router needs to know how close the cells
can be, which is done using the prBound layer. Using a single layer for determining boundaries speeds
up the routing process, and also accounts for layers (like the n-well) which can overlap, and layers (such
as metal layers with differing nets) which must be spaced out.
nwell: Corresponds to the region which is to ion implanted with a n-type doping, mainly for use by ptype transistors. This layer is used to create the N-Well layer (NW). The digitized area on the layout
forms the clear area on the mask (indicating that that opaque mask pattern is the inverse of the pattern
drawn on the layout).
active: Corresponds to the active area. Not used during manufacturing, but is used to signal the
location of doping to the design tools.
Poly1: Corresponds to the location of the lowest polysilicon level, which is usually used for gates of
MOSFETS. This corresponds to the Poly-1 (PO) mask layer, whose mask is formed by converting the
drawn shapes on the layout into the dark areas of the mask.
nplus: Corresponds to regions that will receive n+ (ie. donor) type doping. The mask that this layer
corresponds to is the N+ S/D implant (NP), whose clear area is formed from the digitized layout region.
pplus: corresponds to regions that will receive p+ (ie acceptor) type doping. The mask that this layer
corresponds to is the P+ S/D implant (PP), whose clear area is formed from the digitized layout region.
contact: indicates area where the oxide layer above the substrate (or above a polysilicon layer) will be
etched. This will allow for ohmic contacts to be made to the substrate for tie-downs, MOSFET terminals
and substrate biasing when the metal layer is etched on. This, of course, assumes that the contacts will
be made over p+ or n+ regions; otherwise, Schottky diodes will be made. The contact layer corresponds
to the contact (CO) mask layer, whose clear area is formed from the digitized layout pattern.
metal1: indicates areas where the first metal layer will be placed (and not etched off). If there are any
contact cuts to the substrate or to the poly layer, the metal will form connections to those layers. This
layer corresponds to the Metal-1 (M1) mask layer, whose dark areas are formed from the layout
patterns.
metal1 (pin): The pin layer does not physically correspond to any manufactured mask (although the
metal1 pin layer must be enclosed by shapes in the metal1 (dg) layer). However, it is required to
indicate connectivity to the layout tool. In a particular cell (such as the inverter), connections that must
be made to external modules are indicated by objects called pins. Each pin is created from a shape in a
pin layer. In the verification stages, the layout-vs-schematic (LVS) check will check that cells are
connected together properly. The correct placement of pins is crucial for this check to work properly, as
they form correspondence points to give the tool a starting point.
via12: indicates areas where the oxide layer placed above metal1 will be etched. This will allow
connections to be made from metal1 to metal2. This layout layer corresponds to the Via1 (VIA1) mask,
whose clear area is formed from the layout pattern.
metal2: indicates areas where the second metal layer will be placed (and left on). Like with the metal1
layer, the metal2 layer will fill in any holes in the oxide layer (created by via12) to create vias to allow
connections to be made between metal layers. Similar to the metal1 layer, the metal2 layer
corresponds to the Metal-2 (M2) mask layer, whose dark area is formed from the layout patterns.
metal2 (pin): Indicates the location of pins made using the second metal layer as correspondence points,
similar to what is done to the metal1 (pin) layer. Likewise, it does not correspond to a mask layer.
3. Explain all the DRC errors encountered in Sections 3.13-3.17. Refer to the cmosp35 documentation
when explaining the error.
As can be seen in Figure 2, 2 different types of errors and 1 type of warning was encountered. The
explanations of each can be found in the process documentation. The following is an elaboration of
each error type, and a discussion about how they can be fixed.
Figure 2 DRC errors encountered in the layout of the inverter (taken from the assignment page)
M1. S. 1 metal1 spacing < 0.45
This rule discussed the minimum distance between two separate pieces of metal1, which must be at
least 0.45 um at its closest point. To fix this error, several things can be done: the spacing between the
metal shapes can be increased, one of the shapes can be removed, or the shapes can be joined together
(although care must be taken to avoid a similar notch error). Of these, usually the first solution is the
most practical. The details can be found on page 29 of the process design rules (page 30 in the pdf file).
OD.C.3 ndiff spacing to hot nwell < 2.60
A “hot” n-well is defined as an n-well that is not connected to the highest voltage (ie. VDD). Similarly, a
“cold” n-well is defined as an n-well that is connected to the highest voltage. In this case, the rule is
about the spacing from the n+ diffusion (“ndiff”) to the n-well. To fix this, the nwell must be biased
appropriately (since the minimum distance to a “cold” n-well is only 1.2 um) or the distance should be
increased. Since the error occurs in a standard cell, the only possible solution is to bias the well. To tell
the DRC tool that the well is biased to vdd, a pin must be created in the current cell with the name
“VDD!” (the “!” indicates a global net). Other possible names include “vdd” and “VDD”; in fact, it
appears that the DRC tool will allow any pin name that has the characters “vdd” in them. The tool is
somewhat case insensitive, although the names “vdD”, “vDD” and “vDd” are not acceptable. The details
can be found on page 11 of the process design rules (page 12 on the pdf file), while the discussion of
hot/cold n-wells can be found on page 6 of the process design rules (page 7 in the pdf).
Warning: substrate/well soft connected
This error comes from the fact that the substrate has either been left unconnected, or that it hasn’t
been connected to a net. Ideally, the substrate is connected to the lowest possible voltage (in an n-well
process). In the standard cell, this has been done by connecting the substrate to vss. However, this
must be indicated at the current cell as well. This is done by placing a pin in the current view,
connecting the net to “VSS!” (or any similarly spelled name, similar to the previous case).
This warning also applies to n-wells as well, which should be connected to VDD. In this particular
instance, fixing the previous error will also correct this warning as it applies to the n-well.
Discussion about this warning is not found in the process design rules, although the warning itself
describes enough to understand what is wrong.
After all these changes were made, another DRC check was made to ensure that all problems had been
fixed. This can be seen in Figure 3.
Figure 3 Results of DRC check after all changes were made, indicating that errors/warning were fixed
4. Explain the DRC errors found in Section 3.18, and explain what you did to fix the errors.
The errors shown in section 3.18 are the same as those encountered in 3.17 (only with the metal spacing
error removed). Thus the explanations and solutions discussed in the previous section are applicable to
this one.
5. From Part 4, submit your custom schematic and custom layout. Also submit the LVS report
generated by Cadence. Discuss any DRC errors you made (not all of them, just give a few examples).
Also discuss any LVS errors and how you fixed them.
The schematic of the inverter can be seen in Figure 4, while the layout of the inverter can be seen in
Figure 5.
Figure 4 Schematic of the inverter
Figure 5 Layout of the inverter
Some of the DRC errors encountered and their respective solutions are discussed in the following:
CO.E.2 poly1 overlap of contact < 0.20
This error was obtained from a contact between M1 and poly1. Although the poly1 layer surrounded
the contact rectangle, the edge of the poly was too close to the edge of the contact, yielding this error.
This was fixed by expanding the poly, such that the edges were at least 0.2 um away from the contact.
M1. S. 1 metal1 spacing < 0.45
Like in the previous section, this error was obtained due to the presence of two pieces of metal1 that
were too close to each other. In this case, this was from the drain connections between the two
transistors and the gate connections. This error was remedied by moving the pieces of metal further
away from each other.
After the design passed the DRC test, an extracted view was generated. Figure 6 shows the results after
the extraction command was run, showing that no errors were encountered. The LVS log can be seen
in Figure 7. No errors were encountered when this was done, but for discussion purposes, some
common errors were introduced afterwards to allow for some discussion. This was done by resizing the
PMOS transistor in the layout, which resulted in breaking the source connection to VDD.
Figure 6 Extraction log showing no errors.
Figure 7 LVS log showing no errors
? MOS width mismatch: 1.2e-05(extracted) vs 1.5e-0.5(schematic).
This error indicates that a parameter is mismatched. In this case, it is the width of gate of a transistor.
In order to fix this error, the parameters in one of the views must be changed to match the other.
Which one is selected is up to the designer, since either one may be correct. In this case, the schematic
is correct, so the error can be fixed by changing the layout PMOS width back.
? Net /5 merged with /vdd
This message indicates that two nets found in the layout view are connected together in the schematic
view (since this error was found in the LVS log pertaining to the layout). In this case, the two nets picked
out are /5 and /vdd, which are connected together and labeled as /vdd in the schematic. This error can
be fixed by connecting the two nets together in the layout view, or by disconnecting them in the
schematic. Since in this case, the schematic view is correct, the best option to fix the error is the first
one.
? Terminal vdd is floating in the layout
This error was received in the layout part of the LVS log. It indicates that the pin labeled “vdd” is not
connected to anything. As such, it indicates something similar to the previous error, but this error is
more focused on identifying an unconnected pin, rather than two nets that should be connected but are
not.
6. From Part 5, submit your custom schematic and custom layout. Also submit the LVS report
generated by Cadence. Discuss any DRC errors you made (not all of them, just give a few examples).
Also discuss any LVS errors and how you fixed them.
Figure 8 shows the schematic view of the multi-gate circuit used for the custom layout, while Figure 9
shows the layout of the circuit. DRC and LVS tests were successfully run on the schematics and layouts.
All of the logs can be seen in Figure 10, Figure 11, and Figure 12.
Figure 8 Schematic of the multi-gate circuit
Figure 9 Layout of the multi-gate circuit
Figure 10 DRC log of multi-gate circuit
Figure 11 Extraction log of multi-gate circuit
Figure 12 LVS log of multi-gate circuit.
Some of the DRC errors encountered included the following:
OD.C.3 ndiff spacing to hot nwell < 2.60
Warning: substrate/well soft connected
These two errors were discussed earlier in this assignment. They resulted due to the fact that the
power supply rails were accidentally left unconnected. Creating pins on the top and bottom rails to
VDD! And VSS! Respectively resolved this error.
M2.S.1 metal2 spacing < 0.50
This error was similar to the one encountered earlier, only with metal 2 spacing being an issue as
opposed to metal 1. The spacing between the upper layer metals is larger (0.50 um in this case as
opposed to 0.45 um) which takes into account that the precision of higher layers is lower than that of
lower layers. This is usually due to the upper layers being thicker, as well as the increasing unevenness
of the top surface with increasing number of layers.
Some of the LVS errors encountered include the following:
? Net /10 merged with /11