Experiment#3
Karnaugh Map, NAND & NOR Implementation
Experiment #3
Karnaugh Map
NAND & NOR Implementation
3.1 Objectives
1- Circuit simplification with Karnaugh map.
2- To implement different Boolean functions using NAND gates only.
3- To implement different Boolean function using NOR gates only.
3.2 Background
The Karnaugh Map
Boolean algebra can be applied to simplify a Boolean expression, but for
highly complex functions, finding the best expression is very difficult because:
 The simplification procedure is awkward since it lacks specific rules to
predict the next step.
 It is also difficult to determine whether the simplest expression has been
achieved.
We can conclude the Karnaugh Map method as follow:1- Map the truth table into a Karnaugh map.
2- For each 1, circle the biggest block that includes that 1.
3- Write the product that corresponds to that block.
4- Sum all of the products.
Note: If your goal is the minimum sum-of-products form you will be covering
1’s (as the previous steps).
 If your goal is the minimum product-of-sums form you will be covering
0’s.
NAND and NOR Implementations
Digital circuits are more frequently constructed with NAND or NOR gates
than AND and OR gates. NAND and NOR gates are easier to fabricate with
electronic components and are the basic gates used in all IC digital logic families.
So many rules and procedures have been developed for the conversion from
Boolean functions given in terms of AND, OR and NOT into equivalent NAND
and NOR logic diagrams.
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Experiment#3
Karnaugh Map, NAND & NOR Implementation
I- NAND Implementation
The rule for obtaining the NAND logic diagram from a Boolean function has
two ways:
A) Two-level implementation:
1- Simplify the function and express it in sum of products.
2- Draw a NAND gate for each product term of the function that has at
least two literals. The inputs to each NAND gate are the literals of the
term. This constitutes a group of first-level gates.
3- Draw a single NAND gate (using AND-inverter or inverter-OR graphic
symbol) in the second-level, with inputs coming from outputs of the
first-level gates.
4- A term with a single literal requires an inverter in the first level or may
be complemented and applied as an input to the second-level NAND
gate.
NOR Implementation
The NOR function is the dual of the NAND function. For this reason, the rule
for obtaining the NOR logic diagram form a Boolean function is similar to the
NAND rule except that the simplified expression must be in the product of sums
and the terms for the first level NOR gates are the sum terms.
To obtain the simplified product of sums from a map it is necessary to combine
the 0’s in the map and then complement the function.
A) Two-level NOR implementation procedure
a) Simplify the function in product-of-sums form
b) For sum terms with 2 or more literals, use the same input
c) For sum terms with a single literal, invert the input
d) Draw NOR-NOR as if OR-AND implementation
PRELAB:
Read the procedures carefully and:
1.
2.
3.
4.
Do part I (a), (b), and (c).
Do part II (b).
Do part III (b).
Do part IV (a), (b), and (c).
Draw the circuit connection in both logic and pin diagram. (make it clear
as possible even you can use colors).
3.4 Lab Work
Equipments:
1- 74x00 2-input quad NAND gates.
2- 74x02 2-input quad NOR gates.
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Experiment#3
Karnaugh Map, NAND & NOR Implementation
3- 74x04 hex inverter.
4- 74x08 2-input quad AND gates.
5- 74x32 2-input quad OR gates.
Part I :
Karnaugh Map
Given the function f1(A,B,C) =∑(1,3, 4,5,7).
a) Derive the truth table for f1.
b) Simplify f1 using K-map.
c) Show in logic diagram and schematic diagram the circuit connections of
the simplified function f1.
d) Connect the circuits in part (c) and verify the truth table of part (a).
Part II :
NAND Gate Implementation
a) Using the steps of NAND implementation with two-level, implement the
function f1 in part I using NAND gates only.
b) Show in logic diagram and schematic diagram the circuit connections.
c) Connect the circuit in part (b) and derive the truth table experimentally and
show that it is the same as that in part I.
Part III :
NOR Gate Implementation
a) Using the steps of NAND implementation with two-level, implement the
function f1 in part I using NOR gates only.
b) Show in logic diagram and schematic diagram the circuit connections.
c) Connect the circuit in part (b) and derive the truth table experimentally and
show that it is the same as that in part I.
Part IV:
Circuit Design
A switching network has two control inputs (C1,C2) , two data inputs
(X1,X2), and one output Z.
If C1 = C2 = 0, the output is Z = 0.
If C1 = C2 = 1, the output is Z = 1.
If C1 =1 and C2 = 0, the output is Z = X1.
If C1 = 0 and C2 = 1, the output is Z = X2.
C1
C2
X1
Z
X2
a) Derive a truth table for Z.
b) Use a Karnaugh map to find a minimum AND-OR gates network to realize
Z.
c) Draw in logic diagram and schematic diagram the circuit connections of Z.
d) Connect the circuit in part (c) and verify the truth table.
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Experiment#3
Karnaugh Map, NAND & NOR Implementation
Exercises:
1. Use a Karnaugh map to find the minimum (SOP) & (POS) form for the
expression:
F(A,B,C,D) = AB’ + AB’C’D + CD + BC’D + ABCD
Then implement the function with NAND gates only.
2. Use a Karnaugh map to find the minimum (SOP) & (POS) form for the
expression:
F(A,B,C,D) = A’B(C’D’+C’D)+AB(C’D’+C’D)+AB’C’D
Then implement the function with NOR gates only.
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