DET
Electronics
Analogue & Digital Electronics
(Advanced Higher)
7071
June 2000
HIGHER STILL
Electronics
Analogue & Digital Electronics
Advanced Higher
Support Materials
CONTENTS
OUTCOME 1
Analyse operational amplifier circuit applications
Performance Criteria (a) and (b)
OUTCOME 2
Analyse and use analogue integrated circuits in specific applications.
Performance Criteria (a) and (b)
OUTCOME 3
Minimise a Combinational Logic Circuit and
Programme a PLD
Performance Criteria (a) and (b)
OUTCOME 4
Analyse and test sequential logic devices
Performance Criteria (a) and (b)
APPENDIX A
Normalized tables for second order filters
APPENDIX B
Second order filters
APPENDIX C
Phase locked loop
APPENDIX D
Commutative laws
DET: Electronics: Analogue & Digital Electronics (Advanced Higher)
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DET: Electronics: Analogue & Digital Electronics (Advanced Higher)
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OUTCOME 1
ANALYSE OPERATIONAL AMPLIFIER CIRCUIT APPLICATIONS
PERFORMANCE CRITERIA (A) AND (B)
Introduction to operational amplifiers
The operational amplifier (op-amp) is a linear integrated device which has certain
characteristics which make it useful for applications such as filters, comparators and
amplifiers. Some of the ideal characteristics are listed below:
 infinite voltage gain
 infinite bandwidth
 infinite input impedance
 zero output impedance.
Infinite voltage gain is not desirable in an amplifier as it causes positive feedback and
instability hence the practical op-amp provides negative feedback in its closed loop
configuration in order to restrict this gain. However because of the high gain of the
amplifier, saturation occurs at low input voltages and this characteristic is used in
applications such as comparators which can determine when an input voltage exceeds
a certain level.
As has been mentioned a practical op-amp has a very high input impedance and a very
low output impedance. This is useful in matching a load and source as it prevents
loading effects.
As the op-amp has two inputs it can be used as an inverting amplifier, non-inverting
amplifier and as a differential amplifier. The latter configuration is useful in
applications where the difference of two input signals is required.
Operational amplifier applications
The three basic applications which will be considered in this unit are:
1. 2nd order filters
2. window comparators
3. difference amplifiers.
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1. Second order filters
Active filters
In electronic terms a filter is a circuit or device which attenuates some frequencies
while allowing others to pass. They generally come in four types namely low pass,
high pass, bandpass and bandstop. In this unit the low pass and high pass filters will
only be considered.
An active filter consists of an active device, such as an op-amp, together with a
passive filter. Hence before looking at active filters it is informative to consider
passive filters which determine the frequency response of the active filter as a whole.
Simple passive filters use reactive components, such as capacitors and inductors
together with resistors to create low, high or bandpass frequency responses. In this
unit, however we will concentrate on RC filters as they are generally easier to design.
(Inductors have a dc resistance and also capacitance can manifest itself at higher
frequencies between the turns of the coil. Both of these conditions cause tuning and
frequency response problems.)
The low and high pass passive filters together with their frequency responses are
shown below.
C
R
Input
Output
Input
Output
C
R
Gain
(dB)
Gain
(dB)
3 dB
3 dB
Cut-off
Cut-off
20 dB roll-off
20 dB roll-off
Frequency
Low Pass
Frequency
High Pass
Figure 1
Note that this is a first order passive filter and when this is combined with an op-amp
it becomes an active filter which produces a similar frequency response but the gain
can now be altered by introducing gain setting resistors, see figure 2.
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C
R
Input
Output
Ra
Input
Ra
R
C
Rb
Rb
Low Pass Filter
Output
High Pass Filter
Figure 2
Second order filters are more frequently used and these can be designed by connecting
two first order filters in cascade to give a roll-off of 40 dB/decade. However finer
tuning and gain setting can be achieved by using a circuit called the Sallen-Key circuit
which has a roll-off of 40 dB/decade. This circuit will be discussed in the next
section.
Filter responses
It has already been mentioned that there are four types of filters but there are also
various types of frequency response available. Two of the most frequently used are
known as the Butterworth and Tchebysheff responses and the high pass response for
these two types are shown below.
3 dB
0.5 dB
Passband gain
Passband ripple
3 dB
Gain
(dB)
Passband gain
Passband
Gain
(dB)
Passband
Cut-off
Frequency
Frequency
Frequency
Cut-off
Frequency
(fc)
Butterworth Response
Ripple
Frequency
(fr)
Tchebysheff Response
Figure 3
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As can be seen from this figure the two responses are quite different. The Butterworh
type has what is called a maximally flat response in the passband. Hence there is no
ripple in this type of filter and the cut-off frequency is generally taken at the 3 dB
level as shown. The maximally flat response of the Butterworth filter is good at
frequencies around zero hertz, but it is poorer near the edge of the passband. The
Tchebysheff filter can solve this problem.
As can be seen the Tchebysheff response contains a ripple in the passband which can
be a minor disadvantage. However the attenuation increases more rapidly outside the
passband than the Butterworth and the greater the ripple the more selective the filter.
The pass band is not so clearly defined but is generally taken from the point where the
highest frequency peak ripple occurs. If we consider figure 3 which has a 0.5 dB
ripple and the ripple frequency is 1 kHz then its response would be given as + 0.5 dB
from 1 kHz onwards with a rapidly increasing attenuation for frequencies less than 1
kHz. The order of a Tchebysheff filter is determined by the number of ripple peaks.
The damping factor
The damping factor (D) of an active filter determines the type of frequency response
which will be achieved i.e. Butterworth or Tchebysheff. Basically the damping factor
affects the filter response by using the negative feedback action. If the output voltage
increases or decreases this is offset by the negative feedback action. This will make
the response flat if the damping factor is set correctly. The damping factor is given
as:
DF  2 
Ra
Rb
Ra
 2  DF
Rb
(1)
Where Ra and Rb are the feedback resistors of the op-amp filter.
The value of the damping factor depends on the order of the filter (the number of RC
networks) and the higher the order the faster the roll-off. For example in order to
achieve a second order Butterworth response the damping factor is given as 1.414.
(These values are available from tables.)
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Hence in order to implement this damping factor, the gain setting resistor ratio must
be:
Ra
 2 - DF  2 - 1.414  0.586
Rb
This ratio gives the passband gain of the filter for a non-inverting op-amp
configuration as,
AC  1
RA
 1  0.586  1.586
RB
This gain is given in, what are known as, normalization tables which will be discussed
later.
The sallen-key circuit
This circuit is one of the most common configurations for a second order filter. A low
pass version of this filter is shown in the circuit below.
C1
R1
R2
Input
Ra
C2
Output
Rb
Figure 4
There are two low pass RC networks that provide a roll-off of –40 dB/decade above
the cut-off frequency. One circuit consists of R1 and C1 and the second circuit
consists of R2 and C2. The op-amp acts as a non-inverting amplifier with negative
feedback provided by R3 and R4.
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The cut-off frequency for this filter is given as:
fC 
1
2 R1R2C1C2
(2)
If the components have equal values this becomes:
fC 
1
2RC
(3)
The high pass Sallen-Key circuit is similar to the low pass configuration except that
the components are interchanged. This filter is shown below.
R1
C1
C2
R2
Input
Ra
Output
Rb
Figure 5
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Using normalization tables
There are several methods of designing second order filters but the method used in
this unit will make use of normalization tables. A set of these tables is given in
Appendix A for a range of passband gains. Higher gains are possible using other
tables but as gain is secondary in the design of a filter this set will be suitable for most
applications. The following points should be noted:
 as can be seen, the tables are split into two sections corresponding to low and high
pass filter design and the type of response is indicated
 the component labeling corresponds to the position of each component on the
Sallen-Key circuit
 the tables show normalized values for example, standardised values with a cut-off
frequency of 1 rad/s in this case
 the normalized values must be denormalized before they can be used as practical
values in the circuit. A constant, known as the denormalization factor, is used to
convert the table values and this may be a factor of 103, 104 or 105. The factor 104
will be used in this unit. The denormalization formulae are shown in Appendix B
and these will be used in examples given below.
 the passband gain is given in the left hand column and this is used to determine
the values of RA and RB
 several combinations of components are available in certain cases e.g. a high pass
Tchebysheff 0.5 dB ripple filter has two possibilities when the passband gain is 2.
Example 1
It is required to design a low pass Butterworth filter with a passband gain of 2 and a 3
dB cut-off frequency of 3.2 kHz. Determine the values of all the components.
Solution
Consulting the table gives a choice of components in this case but we will select the
following. The choice is arbitrary.
R1
1.000
R2
1.000
C1
0.874
DET: Electronics: Analogue & Digital Electronics (Advanced Higher)
C2
1.144
9
Using the formulae in Appendix B, these are normalized as follows:
C1 
C1
2fd
0.874
2  3.2  10 3  10 4
 4.35 nF
C1 
C2 
C2
2fd
1.144
2  3.2  10 3  10 4
 5.7 nF
C2 
Also
R   dR
R1  R2  10 4  1
 10 k
As the passband gain is 2 then
R
2  1 a
Rb
Select R b  1 k
 R a  1 k
Example 2
Design a high pass Tchebysheff filter with a 0.5 dB ripple which has a cut-off
frequency of 1 kHz and a passband gain of 1.842.
Solution
Consulting the tables gives the following values:
R1
1.231
R2
1.231
C1
1.000
DET: Electronics: Analogue & Digital Electronics (Advanced Higher)
C2
1.000
10
Using the denormalization formulae and the factor of 104 gives:
1
2  1 10 3  10 4
 15.9 nF
C1  C2 
R1  R2  1.231 10 4
 12.31 k
A 15 k pot. would be selected and set to 12.31 k
The passband gain is unity hence connecting a link between th e
inverting input and the output of the op - amp will satisfy th is requiremen t.
The final circuit is given below.
R1
12.31 k
15.9 nF
15.9 nF
C1
C2
Input
Output
12.31 k
R2
Figure 6
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Tutorial 1
a) Design a first order filter with a gain of 10 and a cut-off frequency of 200 Hz. Use
a 0.05 F capacitor.
b) Using normalized tables design a second order 1 dB ripple Tchebysheff filter with
a gain of 2 and a cut-off frequency of 500 Hz.
c) Using normalized tables design a second order filter having a gain of 1.586 and a
cut-off frequency of 2.5 kHz.
d) A communications system has to pass all frequencies above 10 Hz and below 5
kHz. A flat response is desired with an overall gain of unity and a roll-off of 40
dB/decade. Show how this may be achieved by cascading two filters.
2. Window comparators
Operational amplifiers are frequently used to compare the amplitude of one voltage
with another and for this application the op-amp is used on open loop with the input
voltage to be compared on one input and a reference voltage connected to the other.
Typical circuits are shown below.
+V
+V
R1
R
Vref
Vref
Vout
R2
Vout
Vin
Vin
(b)
(a)
Figure 7
Figure (a) and (b) show different methods of establishing a reference. In one case a
voltage divider network is used while a zener diode is used in the second case. By
using a fixed reference voltage, different voltages may be detected.
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In each case as long as the input voltage (Vin) is less than the reference voltage
(V ref) the output remains at the maximum negative level. When the input voltage
exceeds the reference voltage the output switches to its maximum positive level. This
is shown in the diagram below.
Vi
Vref
0
time
Vout
+Vout(max)
0
time
-Vout(max)
Figure 8
For the voltage divider circuit the reference voltage may be determined by the
expression:
Vref 
R2
 V 
R1  R2
(4)
Where (+V) is the positive supply voltage. Circuit (b) uses a zener diode to establish
the reference voltage and this will depend on the value of the zener operating voltage.
Two individual op-amp comparators may be configured as a window comparator. A
typical circuit is shown below.
+V
R1
+V
VU
D1
A1
Vout
-V
+V
R3
Vin
D2
VL
A2
R2
-V
R5
R4
Figure 9
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This type of circuit detects if a voltage is between two limits called the upper limit
(VU) and the lower limit (VL). These voltages may be achieved by using voltage
dividers or zener diodes as for the single comparator and as long as the input voltage
(Vin) is inside the window, the output of the comparator is at a low saturated level.
When this occurs both diodes are reverse biased and Vout is held at zero volts by the
resistor R5 connected to ground. When Vin rises above VU or below VL, the output of
the appropriate comparator rises to its high saturation level. The diode is then forward
biased and a high level output voltage is produced. This is shown in the diagram
below.
Vu
Voltage window
Vin
Vl
Vout
Figure 10
In order to determine the upper and lower limits of the window comparator, the same
voltage divider formulae are used as for expression (4) except that two voltage
dividers are used. These formulae are given as:
VU 
R2
 V 
R1  R2
5
VL 
R4
 V 
R3  R4
6
Example 3
A window comparator has to be designed for an optical sensor which detects an upper
and lower light intensity. In order to remain within these two limits, the upper limit is
set at 3 V and the lower limit at 1 V. If the supply voltage for the op-amps is + 9 V
calculate the component values required for this window comparator.
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Solution
Select R2=R4=4.7 k
Using the formulae from Appendix B and transposing gives:
R1 

 V  R2   VU  R2 
VU
9 1  3 1
3
 2 k
Similarly
R3 
 V  R4   VL  R4 
V
9 1  11

1
 8 k
3. Difference amplifier
If it is required to produce an output voltage that is equivalent to the mathematical
difference between two input signals this can be achieved by an operational amplifier
functioning in its differential mode. This is sometimes known as a difference
amplifier or a subtractor. The diagram below shows how this is achieved by using the
resistor configuration shown with an operational amplifier.
R4
+V
R3
V2
Vo
V1
R1
-V
R2
Figure 11
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The operation of this circuit is analyzed below.
Using the superposition principle, assume first that V2 is shorted to ground, hence:
V 
R2
V1 where V  is the voltage at the non - inverting terminal
R1  R 2
R 3  R 4   R 3  R 4  R 2 

V1 (virtual earth)
V  
R3
R
R

R
3
2 

 1
Assuming now that V1 is shorted to ground,
So VO1 
VO2 
-R4
V2 (due to the superposit ion principle)
R3
With both signal inputs this gives,
 R  R 4  R 2 
R 

V1   4 V2 ............. (X)
VO  VO1  VO2   3
 R 3  R 1  R 2 
 R3 
This result shows that the output voltage is proportional to the difference between
scaled multiples of the input voltages. Hence to obtain the output:
VO  A C V1  V2 
Where AC depends on the values of the resistors chosen.
Generally the resistors are chosen so that:
R1=R3=R
and
R2=R4=ACR
Substituting these values into equation (X) will give:
A R
A R
A R
 R  A C R  A C R 
V1  C V2  C V1  C V2  A C V1  V2 .......(Y)


(7)
R
R
R
R

 R  A C R 
Note that this type of amplifier minimises the effect of common mode signals. Its
disadvantages are that the input impedance is comparatively low and they are
different for each input. Because of this the common mode rejection ratio is affected
to a considerable extent by the source impedances due to the mismatch.
The impedance to ground can be matched by ensuring that R1 R2  R3 R4.
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Example 4
A difference amplifier has two input voltages given as V1=3 mV and V2=5 mV. If the
output voltage Vo=2 V, determine:
a) the closed loop gain of the amplifier
b) suitable values for the resistors
c) show by means of a schematic diagram how the circuit should be configured for
matching purposes.
Solution
Vo  A C V2  V1 
AC 
Vo
V2  V1 
2
 100
5 - 3
Select R 3  1 k

Now R 4  A C R and R 3  R
R4
1 10 3
 R 4  100 k
100 
Hence R 1  R 3  1 k and R 2  R 4  100 k
For matching purposes the circuit is configured as follows:
R4
100k
+V
R3
1k
R1
1k
V2 =5 mV
V1=3 mV
-V
Vo=2 V
100k
R2
Figure 12
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Example 5
The speeds of two small motors are monitored by two sensors; S1 and S2, and their
outputs fed to a difference amplifier. When the speeds of the motors are correct the
outputs of the sensors are S1=10 mV and S2=15 mV. Under these conditions the
voltage appearing at the output terminals of the difference amplifier is 50 mV.
a) calculate suitable values for the circuit components
b) if the output from S1 increases by 5%, determine the new output voltage.
Solution
Vo  A C S2  S1
Vo
S2 - S1
50

 10
5
AC 
R2 R4

 10
R1 R3
then select R1  15k
 R2  A C R1  10  15  150 k
Since A C 
Tutorial 2
1. Design a window comparator which has to be used in a detector device to measure
voltages between 5 V and 15 V. The supply voltage is + 6 V.
2. Design a window comparator which has to be used as part of a gas pressure
monitor to measure threshold levels between 2V and 5 V. Use a supply of + 10 V.
3. A difference amplifier has two input voltages given by V1=5 mV and V2=8 mV.
If the output voltage is 4 V, determine
a)
the closed loop gain of the amplifier
b)
suitable values for the resistors.
4. The linear displacement of a document scanner is determined by a displacement
sensor compared with the dimensions of the document to ensure that the document
is scanned within the limits of its margins. The distance between the two margins
is represented as an output voltage which is set at thedesired reference level
depending on the size of the document. If the reference level is set at 100 mV
and the linear displacement sensor is set at 80 mV for an output voltage of 20
mV,calculate suitable values for the circuit components.
DET: Electronics: Analogue & Digital Electronics (Advanced Higher)
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OUTCOME 2
ANALYSE AND USE ANALOGUE INTEGRATED CIRCUITS IN SPECIFIC
APPLICATIONS.
PERFORMANCE CRITERIA (A) AND (B)
Introduction
The previous outcome looked at the applications of an operational amplifier which is
a linear integrated circuit. This particular device has many applications but certain
specialised circuits incorporate integration for other applications. Three particular
analogue integrated circuits will be studied in this outcome and these are:
1. the waveform generator (8038)
2. the timer (555)
3. the phase locked loop (565).
1. The waveform generator
A waveform generator is a device which is capable of producing different types of
waveforms over a range of frequencies. The 8038 Intersil circuit is one particular
type acting as a function generator capable of producing sine, square, triangular,
sawtooth and pulse waveforms.
The block diagram
The block diagram of the 8038 is shown below.
+V
Current Source 1
Comparator
1
Comparator
2
C
Current Source 2
Flip-Flop
Gnd
Buffer
Sine
Convertor
Buffer
Triamgular Wave
Square Wave
Sine Wave
Figure 13
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The external capacitor C is charged and discharged by two current sources as shown
in the block diagram. Current source 1 is on continuously while current source 2 is
switched on and off by the flip-flop. Assuming that the second current source is off
and the capacitor is charged with a current I, the voltage across the capacitor rises
linearly with time. When the voltage reaches the level of comparator 1, which is set
at 2/3V+, the flip-flop is triggered and releases the second current source which
normally carries a current of 2I. Hence the capacitor is discharged with a net-current
(I) and the voltage across it drops linearly with time. When it has reached the level of
comparator 2, which is set at 1/3V+, the flip-flop is triggered into its original state and
the cycle repeats itself. Buffering and a sine wave convertor are used to obtain three
waveforms from this basic circuit.
Designing a functional circuit
A practical circuit design for a waveform generator using this integrated chip is shown
below together with the pinout diagram.
V+
R
B
RA
RL
SINE WAVE
1
ADJUST
5
4
7
6
9
Square Wave
8
8038
3
Triangular Wave
2
10
11
C
Sine Wave
12
14 NC
13 NC
SINE WAVE
12 ADJUST
SINE WAVE 2
OUT
TRIANGLE 3
OUT
DUTYCYCLE
FREQUENCY
ADJUST
4
11 V- OR GND
5
V+
6
FM BIAS
7
10 TIMING
CAPACITOR
9 SQUARE WAVE
OUT
8 FM SWEEP
INPUT
ICL 8038
82k
PINOUT DIAGRAM
-V or Gnd
Figure 14
The formulae used in the design of this circuit are given in Appendix C. However
certain points should be noted:
 RA, RB and C are the timing components.
 The distortion of all the waveforms can be altered by using two separate
adjustable resistors RA and RB, using the highest power supply range available(+
15 V) and keeping the maximum currents relatively large (1 mA or 2 mA)
 The frequency range is from 0.001 Hz-300 kHz but the device is best operated
below 200 kHz otherwise distortion occurs in the triangular and sine waves.
 To avoid drift due to temperature variation pins 7 and 8 should be connected.
 The 8038 runs hot at +15 V because it is a resistive device.
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



The generator can be operated from a single power supply (10 V to 30 V) or a
dual power supply (+5 V to+15 V). A dual power supply has the advantage that
all the output waveforms move symmetrically about ground.
In order to reduce distortion in the output waveform an 82 k resistor is
connected between pins 11 and 12.
For a particular output frequency there is a large range of RC combinations, but
there are charging current limitations which are dependent on the power supply
voltages and the value of RA and for this reason optimum performance is achieved
for charging currents in the range 10 A to 1 mA. If pins 7 and 8 are connected
together the magnitude of the charging current due to RA is given by the formula
shown in Appendix C. (Note that a similar calculation is required for RB).
The capacitor should be chosen at the upper end of its possible range.
Example 6
A waveform generator has to be designed to give an output frequency range of 10 Hz
– 100 kHz with a 50% duty cycle. If the power supply is + 10 V, and the charging
current has to be restricted to 440 A, determine the values of the timing components.
Since the charging current has to be 440 A then:
I
0.22 V - - V 
RA
0.22  20
 10 k
440  10 6
R B will also be 10 k (50% duty cycle)
R A 
The capacitor should be chosen at the upper end of its possible range i.e.for
the lower end of the frequency range.
0.33
0.33
C 
 4
 3.3 F
Rf
10  10
Example 7
A waveform generator using an 8038 has to be designed for a frequency range of
of 200 kHz and a duty cycle of 60%. A power supply of + 15 V is chosen for
maximum stability and the timing capacitor is selected as 3000 pF. Determine the
values of the timing resistors.
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Solution
Since the top end of the frequency range is 200 kHz then:
1
1

 5 s
f 2  10 5
 T  T1  T2  5 s
T
Hence T1  3 s and T2  2 s (60% duty cycle)
C  3000 pF
0.66  T1
R A 
C
0.66  3  1012

 660 
10 6  3  10 3
Since T2  2 s and
T2 
R A R BC
0.662R A  R B 
then finding R B
660R B  3  10 3
2

10 6 1012  0.662  660  R B 
2
R B 
66  R B  3
661320  R B 
174240
 528 
330
DET: Electronics: Analogue & Digital Electronics (Advanced Higher)
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2. The timer
The 555 timer is a versatile integrated circuit with many applications. Its block
diagram is shown below.
+Vcc
Upper Comparator
Thresh.
Flip-Flop
Decoupling
Output Buffer
R
Q
Lower Comparator
S
Vout
Trig.
Discharge
Discharge
Path
Transfer
+Vcc
Figure 15
The 555 timer consists of two comparators, a flip-flop , a discharge transistor and a
resistive voltage divider.
The voltage divider is used to set the voltage comparator levels and as all three
resistors have the same value, the upper compartor has a reference level of 2/3 VCC
while the lower comparator has a reference level of 1/3 VCC. When the trigger
voltage goes below 1/3 VCC, the flip-flop sets and the output goes to its high level.
The threshold is connected to an RC timing circuit and when the external capacitor
voltage exceeds 2/3 VCC, the upper comparator resets the flip-flop and this in turn
switches the output back to its lower level. When the device output is low, the
discharge transistor is turned on and this provides a discharge path for the external
capacitor. Hence this operation enables the timer to be configured as an astable or
monostable device. The astable mode will be considered in this unit.
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Designing a functional circuit
The formulae required to design an astable circuit using a 555 timer are given in
Appendix C but a typical configuration is shown below.
+Vcc
RA
8
4
7
R
B
6
555
Vout
3
GND
1
8
TRIG.
2
7 DISCHARGE
Vout
3
6
5
THRESH.
5 Decoupling
Capacitor
RESET 4
2
+Vcc
555
PINOUT DIAGRAM
1
Decoupling
Capacitor
(Optional)
C2
C
1
Figure 16
The following points should be noted about this integrated circuit when used to meet
the requirements of a particular specification:
 the minimum recommended values for the timing resistors are RA= 5k and
RBk
 the maximum supply voltage is +18 V
 the control voltage pin (5) may have to be decoupled to ground using a 10 nF
capacitor in order to improve stability
 the minimum duty cycle using the recommended values of components is about
62%. However by adding a diode across RB this may be extended from 5 to 95%.
The expression used for the duty cycle under these circumstances is:
Duty Cycle 


RA
 100
RA  RB
(8)
duty cycles of about 50% can be achieved if RB>>RA
the type of capacitor used for the timing capacitor (C1) should be silvered mica,
polycarbonate, polystyrene or polypropylene, but not electrolytic types as the
leakage level is too high.
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Example 8
A timer circuit has to be designed to give a clock frequency of 10 kHz. If a duty cycle
of 55% is required calculate all the component values.
Solution
f
1
T
1
 100 s
10 4
For 55% duty cycle
T1
 0.55
T1  T2
T 
0.55 100
 55 s
10 6
 T2  45 s
 T1 
If C1  4.7 nF is selected then
T2  0.7 R B C1
R B 
f
T2
45 10 9
 6
 13.7 k
0.7  C1 10  0.7  4.7
1.44
R A  2R B C1
 2 10 4 13.7  4.7 10 3 

1.44  
9
10

  3.2 k
R A 
4.7 10 4
10 9
DET: Electronics: Analogue & Digital Electronics (Advanced Higher)
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Example 9
A 555 timer has to produce a square wave output with a 40% duty cycle and a
frequency of 50 Hz. Determine the component values required for this specification.
State what modification may have to be made to the final circuit.
Solution
f
1
T
1
 20 ms
50
For 40% duty cycle
T 
T1
 0.4
T1  T2
0.4  20
 8 ms
10 3
 T2  12 ms
 T1 
If C1  2 F is selected then from Appendix C
T2  0.7 R B C1
R B 
f
T2
12  10 6
 3
 8.6 k
0.7  C1 10  0.7  2
1.44
R A  2R B C1
 2  50  17.2  2  10 3 

1.44  
10 6

  20 k
R A 
2  50
10 6
The inclusion of a diode may be required across R B in order
to obtain the 40% duty cycle within th e constraint s of the
integrated circuit.
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3. The phase-locked loop
The phase locked loop (PLL) is a form of closed loop control device which consists of
a phase detector, low pass filter and voltage controlled oscillator (VCO). It has many
applications such as modems, tone decoders, frequency synthesis, signal restoration in
television sets and a technique known as frequency shift keying (FSK).
The basic block diagram is shown below.
(fs+fo)
Input
(fs)
Low
Pass
Filter
Phase
Detector
(fs-fo)
Amp
Output 1
(fo)
Voltage
Controlled
Oscillator
Output 2
Figure 17
Basically the PLL produces a frequency of its own (fo) from the VCO which locks
onto an incoming signal (fs). It then tracks this signal for any variation in frequency
and produces a correction voltage which brings the reference signal back on track.
The phase detector compares the phase of the VCO with the incoming reference
signal, giving an output proportional to the difference in phase. This is then filtered to
remove unwanted high frequency components, and the output from the low pass filter
is used to control the frequency of the VCO, locking it to the incoming signal.
It should be noted that there is only a difference in frequency between two signals
when the phase is changing between them. When the VCO signal is locked to an
incoming reference a steady d.c. error voltage is applied to the VCO and this is
proportional to a constant phase difference between the two signals. Hence there is no
actual phase change and the frequency of the VCO must be exactly the same as the
reference.
Consider the circuit with no applied signal. There will be no error voltage at the
output of the phase detector, and the VCO will run at its natural or free-running
frequency (fo). If an input is applied with a frequency (fs) there will be an error
voltage generated by the phase detector which is proportional to the phase difference
between the two signals. This output consists of sum and difference signals and is
filtered through a low pass filter to leave the difference frequency which is amplified
and applied to the control point on the VCO. The error voltage is such that it reduces
the phase, hence the frequency difference between the two signals. Once the loop has
locked, the frequency of the oscillator will be exactly the same as that of the reference
signal, but there will be a net phase difference which is necessary to generate the
required error voltage to keep the oscillator running at the reference frequency.
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When no signal is applied to the PLL it will have no error voltage applied to the
oscillator. If a signal is applied and swept towards the oscillator frequency, the phase
detector will generate the sum and difference frequencies. If the difference frequency
– which produces the error voltage – falls outside the passband of the low pass filter
no correction will be applied to the oscillator, but as the reference is swept nearer the
oscillator frequency there comes a point where it does fall within the passband and
causes the loop to lock. Therefore, what is called the capture range of the loop can be
defined as the frequency range over which it can gain acquisition. This range depends
largely on the characteristics of the first order low pass filter. Once the PLL has
achieved capture, it can maintain lock with the input signal over a wider frequency
range called the lock range.
There are two main factors which affect the lock range. First the range over which the
voltage controlled oscillator can swing will be limited and if the reference goes
beyond this lock will be lost. Secondly, the output of the phase detector is sensitive to
both phase and amplitude in most cases. Hence if the signal amplitude decreases, the
phase difference between the two signals must increase to compensate for this.
Therefore at low signal levels the effective lock range is reduced and the phase errors
will be larger.
The voltage controlled oscillator (VCO) is virtually a voltage-to-frequency convertor
in which the output frequency is a direct result of the d.c. phase error voltage.
Generally the VCO incorporates special diodes which respond to a d.c. voltage
applied across them. If this d.c. correction voltage changes then the free running
frequency of the VCO changes. Hence any variation in the reference voltage (fs) will
cause a d.c. voltage to appear across the diode thus altering its output.
Designing a functional circuit
The 565 is a typical PLL working over the frequency range 0.001 Hz-500 kHz. It
comprises a VCO, a phase comparator, an amplifier and a low pass filter. The centre
frequency is determined by the free running frequency of the VCO and this frequency
is determined by an external RC timing network. The low pass filter is formed by an
internal resistor (3.6 k) and an external capacitor.
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A typical design configuration is shown in the figure below.
+V
Ro
C
1
0.001 uF
0.1 uF
1
14 NC
2
13 NC
INPUT
10
8
2
7
6
565
5
3
9
Input
680 ohms
-V
INPUT
1
3
VCO
OUTPUT 4
Outputs
COMPARATOR
VCO
5
INPUT
REFERENCE6
OUTPUT
DEMODULATED7
OUTPUT
4
12 NC
11 NC
10 +V
EXTERNAL
9 CAPACITOR
FOR VCO
8 EXTERNAL
RESISTOR
FOR VCO
565
PINOUT DIAGRAM
680 ohms
Co
-V
Figure 18
The following points should be noted concerning this integrated circuit:
 a dual power supply is used with a range of + 5V to + 12 V
 two resistors of the same value are used at pins 2 and 3. These are required to
avoid any offset voltage at the input. Values between 420  and 1 k are
generally selected
 Ro and Co are the timing components and set the value of the free running
frequency of the VCO
 C1 is part of the passive filter which includes a 3.6 k etched inside the chip
 the frequency of the VCO may be checked by disconnecting the link between
pins 4 and 5 and measuring the frequency at pin 4 with a frequency meter
 the output is normally taken between pins 6 and 7. If the output is distorted this
may be remedied by connecting a resistor between the two pins in order to reduce
the loop gain
 the formulae in Appendix C should be used to calculate the theoretical lock and
capture ranges for a suitable power supply. Note that where formulae are stated as
+ values it is more convenient to keep parameter values in this form. For example
if a lock range is expressed as + 500 Hz, this is the swing on either side of the
centre or free running frequency of the VCO, and it should be incorporated in the
formula as 1000 Hz.
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In order to design the circuit for a particular specification the following procedure
should be used:
a) The free running or centre frequency of the VCO must be set up initially. The
value of this frequency will generally be known and the values of Ro and Comay be
determined from the formula. A suitable value for Co is selected.
b) The specification will give the values of lock and capture range desired for a
particular application, and this will enable the value of the filter time constant ()
to be calculated.
c) The value of C1 may then be calculated.
d) The final step is to determine a suitable power supply which can be determined
once again from Appendix C.
e) The testing of the circuit is carried out by connecting a signal generator to the
input of the chip and sweeping through the desired capture range on either side of
the VCO centre frequency. A voltmeter connected between pins 6 and 7 will
indicate when the device is in lock as the voltmeter should read zero volts. Fine
adjustment of the signal generator may be required for this.
f) Sweeping on either side of the centre frequency will cause the output voltage to
increase from the zero reading until the limit of the capture range is reached. This
will be indicated by erratic readings which show the PLL is operating outside its
lock range.
Example 10
A 565 PLL is designed for use in a wide bandwidth application. If fo==1100 Hz,
fL=+700 Hz and fC=400 Hz, calculate the values of Ro, Co, C1 and a suitable value for
the power supply.
Solution
0.3
fo 
R oCo
Selecting C o  100 nF
Ro 
0.3
0.3 10 9

 2.73 k
f o C o 1100 100
Also
1 2f L
2

2f L
6.28 1400
 

 1.39 10 3 secs
2
2
2f C  6.28  400
fC  
But   3.6 10 3  C1
1.39 10 3
 0.386 F
3.6 10 3
8f
Since
fL   O
VCC
 C1 
then
VCC  
8 1100
 6.3 V
1400
DET: Electronics: Analogue & Digital Electronics (Advanced Higher)
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Example 11
A 565 PPL has to be used for a narrow band specification in order to reduce noise.
The parameters are set at fo=1000 Hz, fL=+500 Hz and fC=+200 Hz. Determine the
required values of the components and also a suitable value of power supply.
Solution
0 .3
R OCO
fO 
Selecting C O  120 nF
RO 
0. 3
0.3
 3
 2.5 k 
f O C O 10  120  10 9
Also
fL  
8f O
VCC
Hence VCC  
8f O 8  10 3

 8 V
fL
10 3
1 2f L
2

2f L
6.28  10 3
 

 9.95  10 4 sec
2
2
2f C  6.28  400
fC  
Also   3.6  10 3  C1
 C1 

3.6  10 3

9.95  10 4
 276.4 nF
3.6  10 3
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Tutorial 3
1. A waveform generator has to be designed to give an output frequency range of
100 Hz to 200 kHz with a 60% duty cycle. If the power supply is + 9 V and the
charging current has to be limited to 350 A, determine the values of the timing
components.
2. Design a timer, using a 555 integrated circuit, which will give a clock frequency
of 1 kHz with a duty cycle of 45%. Determine all the components and draw the
circuit diagram.
3. Determine typical values for a 565 phase locked loop wide bandwidth application
if fo=1 kHz, fL=+800 Hz and fC=300 Hz. Select CO=250 nF.
4. A 565 phase locked loop is used in a narrow band application in order to filter out
noise in a communications system. The parameters are fO=1.2 kHz, fL=+600 Hz
and fC=+500 Hz. Calculate the values of the required components using CO=150
nF and C1=9 nF.
5. Design a 555 timer which has a duty cycle of 50% and would be suitable for a
slow clock frequency of 50 Hz.
6. Design a waveform generator suitable for producing a sine wave output over the
frequency range 20 Hz to 20 kHz with a duty cycle of 50%. The power supply has
to be + 12 V and the charging current has to be limited to 500 A.
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OUTCOME 3
MINIMISE A COMBINATIONAL LOGIC CIRCUIT AND
PROGRAMME A PLD
PERFORMANCE CRITERIA (A) AND (B)
Introduction
Boolean algebra is the mathematics of digital circuits and systems and a basic
knowledge of it is essential in order to analyse logic circuits.
In this outcome the techniques of minimisation are discussed by using truth tables and
Karnaugh maps. However, knowledge of the simplification involved in Boolean
functions is required and for this purpose the basic laws and rules of Boolean algebra
must be known.
Appendix D lists these laws and it can be seen that some are similar to ordinary
algebra but others are peculiar to combinational logic systems.
Example 12
Simplify the following expression using the Boolean laws and rules.
A.B  A.(B  C)  B.(B  C)
Solution
Distributi ve law gives
Rule 7
A.B  A.B  A.C  B.B  B.C
A.B  A.B  A.C  B  B.C
Rule 5
Rule 10
A.B  A.C  B  B.C
A.B  A.C  B
Rule 10
B  A.C
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Example 13
Simplify the Boolean expression:
[A.BC  B.D   A.B]C
Solution
Distributi ve law gives
(A.B.C  A.B.B.D  A.B)C
Rule 8
(A.B.C  A.0.D  A.B)C
Rule 3
(A.B.C  0  A.B)C
Rule 1
(A.B.C  A.B)C
Distributi ve law A.B.C.C  A.B.C
Rule 7
A.B.C  A.B.C  B.C(A  A)
Rule 8
B.C.1
Rule 4
B.C
Example 14
Simplify the Boolean expression:
A.B.C  A.B.C  A.B.C  A.B.C  A.B.C
Solution
Factorise
B.C( A  A)  A.B.C  A.B.C  A.B.C
Rule 6
B.C.1  A.B(C  C)  A. B.C
Rule 4 and 6
B.C  A.B.1  A.B.C
Rule 4
B.C  A.B  A.B.C  B.C  B(A  A.C)
Rule 11
B.C  B(A  C)
Distributi ve and
Commutativ e laws B.C  A.B  B.C
Standard forms of Boolean Expression.
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The previous section dealt with simplifying Boolean expressions, but all Boolean
expressions can be converted into either of two standard forms:
1. the sum-of-products
2. the product-of-sums.
Standardising terms makes minimisation and implementation of a Boolean expression
more systematic and easier to handle.
1. The sum-of-products form (SOP)
A product term is defined as a term consisting of the product (Boolean multiplicationA.B.C) of several variables, and when several terms are summed together (Boolean
addition- A+B+C) the resulting expression is called sum-of-products (SOP).
e.g. A.B+B.C+A.B.C. Note that a single bar cannot extend over more than one
variable
e.g. A.B.C is not permitted but A.B.C is permissabl e.
Standardising sum-of-products expressions
In the previous sections Boolean expressions have been shown in which some of the
variables are missing from certain terms e.g. A.B  A.B.C  A.C. A standard term is
one in which all the variables are present and they are important in constructing truth
tables and simplifying Karnaugh maps.
In order to convert product terms into standard form Boolean rule 6 is used in
Appendix D. (A  A  1)
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Example 15
Convert the following Boolean expression into standard sum-of-products form.
A.B.C  A.B  A.B.D
Solution
A.B.C  A.B  A.B.D
Taking each term and using rule 6
A.B.C(D  D)
A.B.C.D  A.B.C.D
A.B  A.B(C  C)  A.B.C  A.B.C
Each of these terms is now expanded
A.B.C  A.B.C(D  D)  A.B.C.D  A.B.C.D
A.B.C  A.B.C(D  D)  A.B.C.D  A.B.C.D
A.B.D  A.B.D(C  C)  A.B.D.C  A.B.D.C
 A.B.C  A.B  A.B.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D
 A.B.C.D  A.B.C.D  A.B.C.D
2. The product-of-sums(POS)
When several sum terms are multiplied, the resulting expression is a product-of-sums:
(POS). e.g. (A  B  C)(C  D)( B  C  D)
As with the sum-of-products terms a single bar cannot extend over more than one
variable, but more than one variable in a term can have a bar. Also each sum term can
be converted to a standard term by using rule 12.
Example 16
Convert the following Boolean expression into a standard POS form.
(A  B  C)(B  C  D)( A  B  C  D)
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36
Solution
Take one term at a time and apply rule 12
First term
A  B  C  A  B  C  D.D  (A  B  C  D)(A  B  C  D)
Second term
B  C  D  B  C  D  A.A  (A  B  C  D)( A  B  C  D)
The third term is in standard form hence the standard POS form is
(A  B  C)(B  C  D)( A  B  C  D) 
(A  B  C  D)(A  B  C  D)( A  B  C  D)( A  B  C  D)( A  B  C  D)
Implementation of SOP and POS Expressions.
Implementing an SOP expression is achieved by ORing the inputs of several AND
gates. The original expression used in Example 15 may be implemented as shown in
the figure below. Note the use of invertors to compliment the variables.
A
B
1
2
1
2
1
2
13
12
C
A
1
1
2
8
3
2
B
A
B
D
1
9
Y=ABC+AB+ABD
2
1
2
13
12
Figure 19
If it is required to implement a POS expression then this simply requires ANDing the
outputs of several OR gates. Consider implementing the expression:
(A+B)(B+C)(A+B+C)
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This is implemented as shown in the figure below.
A
1
B
2
B
3
1
3
C
2
A
B
C
1
2
8
1
2
13
12
Y=(A+B)(B+C)(A+B+C)
9
Figure 20
Developing truth tables for standard SOP and POS expressions
The standard Boolean expressions developed in the previous section may be
converted to a truth table format. Because the truth table shows the logical operation
of a digital circuit in a concise form they are commonly used in practice. In
developing truth tables from standard SOP and POS expressions the following steps
should be taken:
 list all the possible combinations of binary values of the variables in the
expression
 convert the expression into standard form
 place a 1 in the output column for each binary value that makes the standard
expression a 1 for a SOP expression and a 0 in the output column that makes the
standard expression a 0 for a POS expression
 place a 0 for the remaining binary values for a SOP expression and a 1 for the
remaining binary values for a POS expression.
Example 17
Develop a truth table for the following standard SOP expression
A.B.C  A.B.C  A.B.C
Solution
As there are three variables there will be eight possible combinations of the variables.
The binary values that make the product terms in the expression equal to 1 are:
A.B.C  101 : A.B.C  100 : A.B.C  111
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All other combinations will give a 0 at the output. The truth table is shown as follows.
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
0
0
0
0
1
1
0
1
Example 18
Develop a truth table for the following standard POS expression.
(A  B  C)(A  B  C)( A  B  C)
Solution
The binary values that make the sum terms equal to 0 are:
(A  B  C)  000 : (A  B  C)  101 : (A  B  C)  111
All other combinations will give a 1 at the output. The truth table is shown as
follows.
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
0
1
0
1
1
1
1
0
It can be seen from the above examples that the standard forms of the POS and SOP
expressions may be extracted easily from a truth table.
The karnaugh map
It has already been shown in a previous section that a Boolean expression may be
simplified by using certain rules and laws. This minimises the logic gate circuit but it
requires a knowledge of the Boolean rules. A more convenient method is to use a
Karnaugh map.
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39
The Karnaugh map is similar to a truth table in that all the possible combinations of
the variables are shown in a cellular format. Karnaugh maps can be are generally
used for expressions with two, three, four and five variables. Beyond this the map
becomes difficult to use. A maximum of four variables will be used in this unit,
however it is informative to consider the 3 – variable map as it is structured in a
slightly different way from the 4 – variable type.
The 3 – variable karnaugh map
This map consists of an array of eight cells arranged as shown below.
C
0
AB
00
A
01
A
11
A
10
A
1
C
A
B
C
C
A
B
C
B
C
A
B
C
B
C
A
B
C
B
B
Figure 21
The value of any particular cell is the binary values of A and B on the left in the same
row combined with the binary value of C at the top of the map in the same column.
For example the cell in the bottom right hand corner has the binary value 101.
The 4 – variable karnaugh map
This map consists of sixteen cells arranged as shown below.
CD
01
00
AB
00 A
B
11
10
C
D
A
B
C
D
A
B
C
C
D
A
B
C
D
A
B
C
D
A
B
C
D
D
A
B
C
D
01
A
11
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
10
B
Figure 22
In this case the value of a given cell is the binary values of A and B on the left in the
same row together with the binary values of C and D at the top of the map in the same
column.
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Mapping a sum-of-products expression
As this unit is concerned with 4 – variables we will confine the following discussion
to a 4 – variable Karnaugh map. The mapping process can be considered in two
stages:
 determine the binary value of each of the terms
 place a 1 on the map in the cell having the same value as the term.
Example 19
Map the following expression on a Karnaugh map.
A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D
Solution
A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D
0011 0100 1101 1111 1100 0001 1010
The Karnaugh map will be represented as follows. A few of the terms are shown on
the map.
CD
AB
00
01
11
10
A
1
00
01
1
11
1
1
B
C
D
1
A
B
C
D
1
10
1
Figure 23
Minimisation of SOP expressions using a karnaugh map
It is always desirable to obtain the fewest possible terms and variables in an
expression. This process is called minimisation and only when this is achieved should
the expression be implemented in a logic circuit. The Karnaugh map achieves this by
three distinct steps, namely, grouping the 1s, obtaining the product term for each
group and finally obtaining the minimised expression.
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The 1s are grouped according to the following rules:
 a group of 1s must consist of 1, 2, 4, 8, or 16 cells for a 4 – variable Karnaugh
map
 the largest possible number of 1s in a group is required
 the 1s in a group may be included in another group where overlapping occurs.
These rules are shown in the Karnaugh map below.
CD
AB
00
01
00
11
10
1
1
AC
01
1
1
1
11
1
1
1
1
B
10
1
1
ACD
Figure 24
This diagram shows how the minimum terms are determined for a 4 – variable map.
The following points may be deduced:
 a 1 cell group gives a 4 – variable product term
 a 2 cell group gives a 3 – variable product term
 a 4 cell group gives a 2 – variable product term
 an 8 cell group gives a 1 variable term
 a 16 cell group gives a value of 1 for the expression.
Once the map has been determined the minimum expression can be derived. The
Karnaugh map above yields the minimised expression:
B  AC  ACD
Example 20
Use a Karnaugh map to minimise the following expression:
B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D
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Solution
The first term B.C.D must be expanded to give A.B.C.D  A.B.C.D .
The Karnaugh map is given below.
BC
CD
00
AB
01
11
1
1
00
10
1
D
01
11
1
1
1
1
1
10
1
1
Figure 25
Note that a group of eight and four is formed because of the ‘wrap around’ nature of
the Karnaugh map. Hence the minimised expression becomes D  BC .
Mapping from a truth table onto a karnaugh map
Truth tables have already been discussed and these can now be represented on a
Karnaugh map. Remember that the truth table contains standardised terms and these
will be minimised when transferred to the Karnaugh map. An example is given
below.
CD
A
B
C
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Y
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
00
AB
01
11
00
1
01
1
10
1
AC
1
11
10
1
1
ABC
Figure 26
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Karnaugh map minimisation of POS expressions
Minimisation of POS expressions is carried out in a similar fashion to SOP
expressions except that a 0 is placed in the cell instead of a 1.
Example 21
Use a Karnaugh map to minimise the standard POS expression given below.
(B  C  D)(A  B  C  D)( A  B  C  D)(A  B  C  D)( A  B  C  D)
Solution
The first term is not in standard form so it has to be standardised.
(A  B  C  D) and (A  B  C  D)
The Karnaugh map is shown below.
CD
AB
00
01
11
10
00
01
11
10
0
0
A+B+D
0
0
0
C+D
0
A + B +C
Figure 27
Once again this minimised expression (C  D)(A  B  D)( A  B  C) is equivalent to
the original standardised expression.
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Implementation of logic circuits
Once the minimisation process has been carried out it is a simple matter of designing
the log circuit. Example 21 would be implemented as shown below.
C
D
A
1
2
1
3
2
A 1
2
B
8
D
9
1
2
8
9
1
2
13
12
Y=(C+D)(A+B+D)(A+B+C)
B
C
Figure 28
Performance Criteria (d)
PLD programming
Programmable Logic Devices (PLDs) are more frequently used now than MSI devices
because they reduce the number and cost of devices for a particular design. A PLD
consists of a large number of AND and OR gates which are connected together by
fusible links contained in a matrix form. By blowing these links any logic design can
be implemented from the minimisation methods already discussed.
PLDs are classified into different types such as the Programmable Read-Only
Memory (PROM) which consists of a fixed AND array and a programmable OR
array, the Programmable Logic Array (PAL) which consists of a programmable AND
array and a programmable OR array, and Programmable Array Logic (PAL) which
consists of a programmable AND array and a fixed OR array together with ouput
logic.
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The basic structure of a PAL is shown below. A two variable device has been chosen
for simplicity but PALs may have many inputs and outputs.
A
B
A
B
Fuse Links
1
3
2
1
3
1
2
8
2
1
9
3
2
Figure 29
If a Boolean expression has to be implemented the appropriate fusible links are
blown. An example of this is shown below where a 2-variable SOP expression has to
be implemented.
A
A
B
B
Fuse Links
1
3
2
1
3
2
1
2
8
1
3
9
Y=A.B+A.B+A.B
2
Figure 30
The above diagram indicates the actual simplified structure of part of a PLD device.
However PLDs are complex devices and other components are generally processed
onto the chip such as input buffering to prevent loading effects caused by a number of
AND gate inputs which may be required for a particular implementation.
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Y
A simplified diagram, however, is generally shown and this is illustrated below using
the solution of Example 20.
Product term lines
A
A
B
B
C
C
D
D
1
3
2
1
3
2
1
3
2
1
2
8
9
Y=D+B C
1
3
2
1
3
2
Figure 31
In this diagram each product term (two in this case) is allocated a product term line as
shown. Each product term line for a 4 – variable expression will have eight inputs to
each AND gate.
PLD programming
In order to programme a PLD a computer , a software package (sometimes called a
compiler) and a programmer are necessary.
There are many software packages but they all perform similar functions which are
listed below:
 they process and synthesize the logic design by entering the design from Boolean
expressions or from a truth table (other methods are possible but these are the
most frequently used)
 they convert the entered data into an intermediate file
 they generate the fuse map.
The PLD is inserted in the programmer socket and the logic design is entered into the
computer by means of a source file. Next the type of PLD device, the input and
output pin numbers and variables are entered. The logic expression is then entered in
the form of a Boolean expression or a truth table. The compiler then processes and
translates the file before simulating the software to check the correct operation of the
circuit.
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When the design has been checked and debugged the compiler generates a
documentation file which may include the final logic diagram, a fuse map and a
pinout diagram of the PLD.
The fuse map is then passed to the programmer from the compiler and the
programmer will then blow the required fuses in the PLD to create the final design.
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OUTCOME 4
ANALYSE AND TEST SEQUENTIAL LOGIC DEVICES
PERFORMANCE CRITERIA (A) AND (B)
Introduction to synchronous edge triggered flip-flops
Flip-flops are synchronous bistable devices which means that the output changes state
only at a particular point on the triggering input clock pulse. Hence the output is
synchronized with the clock pulse.
Edge triggering may occur at the negative edge (falling edge) or at the positive edge
(rising edge) of the clock pulse and two commonly used devices which use both types
of triggering are the edge triggered D-type and JK-type flip-flops.
The edge triggered D-type flip-flop
This flip-flop is used to store a single data bit and has only one input namely the D
input. Q always follows the data input D. If the input is high when a clock pulse is
applied to a positive edge triggered device, the flip-flop will SET and a 1 will be
stored on the positive going edge of the clock pulse. If the input is low when the
leading edge of the clock pulse is applied then the flip-flop will RESET and a 0 will
be stored in the device. If a negative edge triggered device is used its operation will
be the same except that the triggering occurs on the falling edge of the clock pulse.
The truth tables for negative and positive going D-type flip-flops are shown below.
D
Q
Q
1
1
0
SET
0
0
1
RESET
Q
Q
1
1
0
SET
0
0
1
RESET
D
CLK
CLK
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The timing diagram for the D-type flip-flop is shown below.
CLK
D
D
Q
C
Q
Q
The edge triggered J-K flip-flop
This is the most common type of flip-flop and as with the D-type it can be negative or
positive edge triggered. However another type of J-K flip flop is the master-slave type
which has the same truth table as the edge triggered type except for the way it is
clocked. This type of flip-flop has two sections namely the master and the slave. The
slave section is clocked on the inverted clock pulses and is controlled by the outputs
of the master section rather than by the external J-K inputs. The master slave type has
largely been replaced by the edge triggered type and this type will be considered in
this unit.
The timing diagram for this device is shown below.
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The timing diagrams show the operation of this device. If the flip-flop is RESET
initially and the J input is high while the K input is low then when a clock pulse
occurs the device will SET. If J is now made low and K high the next leading edge
will cause the flip-flop to RESET. If a low is applied to both the J and K inputs the
flip-flop will stay in its RESET condition (there is no change). When both the J and
K inputs are high the flip –flop will change to its opposite state. This is called
toggling. The truth table below shows the operation of the device.
J
K
0
CLK
Q
Q
0
Q
Q
No change
0
1
0
1
RESET
1
0
1
0
SET
1
1
Q
Q
Toggle
Asynchronous edge triggered flip-flops
The devices discussed in the last section are synchronous types because the data on
the inputs is transferred to the output only on the triggering edge of the pulse.
However most devices also have asynchronous inputs which affect the state of the
flip-flop independent of the clock. The pins are generally labeled preset (PRE) and
clear (CLR). Hence if an active level appears on the preset the flip-flop will SET and
if an active level appears on the clear the flip-flop will RESET. Such a device is
shown below together with some timing diagrams for a particular application.
PRE
HIGH
CLK
Q
J
PRE
CLK
CLR
Q
K
Q
Preset
Toggle
Clear
CLR
Figure 32
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In this example during the first three clock pulses the preset is low. Hence the flipflop is RESET. For the next four pulses the flip-flop toggles as J is high, K is high
and both PRE and CLR are high. For the final clock pulse the CLR input is low thus
keeping the flip-flop RESET.
Performance Criteria (c)
Counters
An application for which JK-flip-flops are frequently used is in counting circuits.
This unit requires the testing of MSI counters but it is informative to design these
circuits with individual flip-flops. Two basic types of counter may be designed
namely asynchronous and synchronous.
Asynchronous counters
An asynchronous counter is one in which the flip-flops do not change states at exactly
the same time. This is because they do not have a common clock pulse applied to
them. The figure below shows a 3-bit asynchronous counter. Note that a 4-bit
asynchronous counter would require four JK flip-flops and a 5-bit counter five JK
flip-flops and so on.
HIGH
J1
CLK
C
K1
Q2
Q1
Q0
J2
C
K2
J3
C
K3
CLK
Q0
Q1
Q2
Figure 33
Note that each time the output is divided by two and that the counter recycles after the
eighth clock pulse. This is characteristic of counters of this type.
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Modulus counters
Binary counters similar to the one just discussed have a maximum modulus which
means they progress through all of the possible states. In the 3-bit counter for
example the counter has eight states while a 4-bit counter would have 16 states and so
on. Hence the maximum number of states is given by 2n where n is the number of
flip-flops. Note that a mod-N counter will count up to (N-1) before resetting.
However counters can be designed so that the number of states can be reduced within
the natural sequence. Consider the 3-bit counter already discussed. If it is required to
redesign this circuit so that it terminated its count at 5 instead of 8, then a method has
to be found which will recycle the counter at the fifth clock pulse. The timing
diagram shows how this can be done. At the leading edge of the fifth clock pulse Qo
and Q2 are both high. Hence taking the outputs of Qo and Q2 to a NAND gate will
achieve this as the output of the gate can then be applied to the CLR inputs of the first
and third flip-flop. This is shown below.
1
HIGH
3
2
5 Decoder
J0
J1
Q1
Q0
C
C
K0 CLR
K1 CLR
J2
Q2
C
CLK
K2 CLR
Figure 34
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A typical 4-bit MSI asynchronous counter is shown below. The 74LS93 actually
consists of four JK flip-flops and by connecting the pins of the chip in a particular
way several modulus values are possible. The two diagrams show the chip connected
as a mod-12 counter and as a decade counter. Note that RO1 And RO2 are resets in
this chip.
CLK A
CLK A
Mod-12 Counter
CLK B
RO1
Mod-10 Counter
CLK B
RO1
74LS93
RO2
74LS93
RO2
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Figure 35
Synchronous counters
Synchronous counters are clocked in a different way from asynchronous counters and,
as will be seen, some logic is also necessary. A 3-bit synchronous counter is shown
below together with the timing diagram.
High
1
J0
J2
C
C
C
K9
2
J1
Q2
3
Q1
Q0
K1
K2
CLK
CLK
Q0
Q1
Q2
Figure 36
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This circuit is different from the asynchronous counter in that the clock inputs are
connected to a common clock and the Q outputs are connected to the J inputs. Also in
order to cycle through the sequence correctly an AND gate is used. The operation of
this circuit is as follows.
Q0 changes on each clock pulse as the counter goes through the cycle and then back to
its original state. This operation is achieved by holding the first flip-flop in the toggle
mode (J0 and K0 connected to High). Q1 goes to the opposite state after each time Q0
is a 1 as can be seen from the timing diagrams. The eighth pulse causes the counter to
recycle and in order to produce this operation Q0 is connected to the J1 and K1 inputs
of the second flip-flop. When Q0 is a 1 and a clock pulse occurs, the second flip-flop
is in the toggle mode and hence changes state. At all other times the second flip-flop
is in the no-change mode. From the timing diagrams Q2 changes state when both Q0
and Q1 are high. These two outputs are connect to an AND gate and the output of this
gate makes the J2 and K2 inputs of the third flip-flop high. At all other times the
inputs of the third flip-flop is held low by the AND gate output and hence it does not
change. The state table for this operation is shown below.
Clock Pulse
Initially
Q2
0
0
0
0
1
1
1
1
0
1
2
3
4
5
6
7
8
Q1
0
0
1
1
0
0
1
1
0
Q0
0
1
0
1
0
1
0
1
0
A 4-bit synchronous counter is an extension of the 3-bit counter and this is shown in
the figure below.
High
1
J0
2
J1
Q0
3
2
J2
Q1
Gate 2
3
C
K2
K1
Q3
J3
Q2
C
C
K0
1
Gate 1
C
K3
CLK
Figure 37
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The pinout diagram of a typical MSI 4-bit synchronous counter is shown below.
Data Inputs
CLR
1
LOAD
9
ENP
7
ENT
10
CLK
2
RCO
6
5
4
3
74LS163
15
Q0
11
12
13
14
Q1
Q2
Q3
Data Outputs
Figure 38
This integrated circuit, as well as functioning as a 4-bit counter has the ability to be
synchronously preset to any 4-bit binary number by applying the correct levels to the
data inputs. When a low state is applied to the LOAD input, the counter will assume
the state of the data inputs on the next pulse so that the counter sequence can be
started with any 4-bit binary number. The CLR resets all four flip-flops. There are
two enable pins labeled ENP and ENT. These inputs must be high for the counter to
cycle through its states. The ripple clock (RCO) goes high when the counter reaches a
count of fifteen. This counter like many MSI counters may be cascaded to obtain
higher modulus values.
Performance Criteria (b)
Shift registers
Registers are used for the storage of digital data but do not generally have a
characteristic sequence of internal states as do counters. They consist of an
arrangement of flip-flops and are used for the storage and transfer of data.
The registers considered here deal with D-type flip-flops and the concept of storing
data in this device is shown below. Positive edge triggering is used throughout this
discussion but of course negative edge triggering may also be used.
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D
D
Q
Q
0
1
0
1
C
C
(a)
(b)
Figure 39
Diagram (a) shows a 1 being applied to the data input. A clock pulse is applied which
stores the 1 by setting the flip-flop. When the 1 on the input is removed, the flip-flop
remains SET and hence the 1 is stored. Diagram (b) show the procedure involved in
storing a 0.
Registers are capable of storing large amounts of data depending on how many flipflops are used. With MSI devices very high storage capacities are possible. Also the
data has to be shifted inside the register as each piece of data is entered. This
operation, together with the types of register used, are shown in the following
diagram. Eight bit registers are used here.
Serial in/Serial out
Shift Right
Parallel in/Serial out
Shift Left
Serial in/Parallel out
Parallel in/Parallel out
Figure 40
As can be seen from this diagram four basic types of register are common but the
serial in/parallel out type will be discussed here. However it is informative to
consider the serial in/serial out shift register as it is simpler to follow the progress of
the data as it is entered.
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The diagrams below will help understand how the data is entered and then shifted out
of the register. A 3-bit register is used for simplicity but the same procedure is used
generally for higher bit registers.
First data bit=1
1
0
0
0
D
1
CLK
0
Second data bit =0
1
First data bit
D
CLK
0
1
4
0
0
0
0
Second data bit
D
CLK
D
2
CLK
0
Third data bit=0
0
5
1
0
0
Third data bit
D
CLK
0
3
D
CLK
6
Figure 41
As can be seen from this set of diagrams a 3-bit digital number 001 is entered into the
register which are initially clear. After the first clock pulse 1 has been entered. The
first flip-flop is reset and the digit is stored. A 0 is then entered at the data input of the
first flip-flop and its output is 0 while the output of the second flip-flop is 1. Hence
after the second clock pulse 01 has been stored in the register. The final digit is then
stored in a similar fashion and at the end of the third clock pulse 001 has been stored.
The bits are removed from the register in a similar manner as can be seen from the
figure above. The fourth, fifth and sixth clock pulses shift the bits serially to the right
and at the end of the seventh clock pulse the register has been cleared.
Serial in/parallel out shift registers
In the previous section the operation of a serial in/serial out shift register was
explained. In this case the data was entered and taken out of the register one bit at a
time. The serial in/parallel out shift register enters the data one bit at a time but all the
bits are available simultaneously at the output.
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An 8-bit serial in/parallel out shift register is shown below.
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLR
DATA
D
D
C
D
C
D
C
D
C
D
D
C
C
D
C
C
CLK
Figure 42
This register uses positive edge triggering and a clear facility is also shown. The
timing diagram is shown below.
CLR
DATA
CLK
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Figure 43
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APPENDIX A
Normalized tables for second order filters
Low pass normalized filter with cut-off frequency of 1 rad/s
FILTER TYPE
Butterworth
0.5-dB ripple Tchebychev
1.0-dB ripple Tchebychev
R1
R2
C1
C2
Gain
1.000
1.000
1.000
0.707
0.812
1.000
1.000
0.701
0.952
1.000
1.000
0.911
1.000
1.000
1.000
1.414
0.812
1.000
1.000
0.940
0.952
1.000
1.000
0.996
1.000
1.414
0.874
1.000
1.000
1.403
0.771
1.000
1.000
1.822
0.938
1.000
1.000
0.707
1.144
1.000
1.000
0.470
0.856
1.000
1.000
0.498
0.967
1.000
1.585
1.000
2.000
2.000
1.842
1.000
2.000
2.000
1.954
1.000
2.000
2.000
High pass normalized filter with cut-off frequency of 1 rad/s
FILTER TYPE
Butterworth
0.5-dB ripple Tchebychev
1-dB ripple Tchebychev
R1
R2
C1
C2
Gain
1.000
0.707
1.000
1.144
1.231
0.713
1.000
1.247
1.050
0.549
1.000
1.066
1.000
1.414
1.000
0.874
1.231
2.127
1.000
1.169
1.050
2.009
1.000
1.034
1.000
1.000
1.414
1.000
1.000
1.000
1.426
1.000
1.000
1.000
1.097
1.000
1.000
1.000
0.707
1.000
1.000
1.000
1.064
1.000
1.000
1.000
1.004
1.000
1.585
1.000
2.000
2.000
1.842
1.000
2.000
2.000
1.954
1.000
2.000
2.000
DET: Electronics: Analogue & Digital Electronics (Advanced Higher)
61
APPENDIX B
Second order filters
C 
C
2fd
Where:
 d is the de-normalization factor which is chosen as 104
 C is the actual circuit va lue
 C is the normalized tables value
 f is the cut-off frequency
R   dR
Where:
 d is the de-normalization factor
 R is the actual circuit va lue
 R is the normalized tables value
f
1
2 R 1 R 2 C1 C 2
A  1
RA
RB
Window comparator
VU 
R2
( V)
R1  R 2
VL 
R4
( V)
R3  R4
Difference amplifier
 R R4
VO   3
 R3
 R 2

 R 1  R 2
R

V1   4

 R3

V2

When R1=R3=R and R2=R4=AR then:
VO=A(V1-V2)
DET: Electronics: Analogue & Digital Electronics (Advanced Higher)
62
APPENDIX C
Phase locked loop
1 2f L
2

where   (3.6  10 3 )  C1
fC  
fO 
1.2
4R O C O
fL  
8f O
VCC
555 Timer
f
Duty Cycle 
1.44
R A  2R B C1
RA RB
T1
100 
R A  2R B
T1  T2
T1  0.7R A  R B C1
T2  0.7R B C1
Waveform generator
R AC
0.66
R A R BC
T2 
0.662R A - R B 
T1 
f
1
1

T1  T2 R A C 

RB
1 

0.66  2R A  R B 
For a 50% duty cycle
0.33
f
where R  R A  RB
RC
0.22 V - - V 
I
RA
DET: Electronics: Analogue & Digital Electronics (Advanced Higher)
63
APPENDIX D
Commutative laws
A+B=B+A
A.B=B.A
The order is not important.
Associative laws
A+(B+C)=(A+B)+C
A.(B.C)=(A.B).C
The order of grouping is not important.
Distributive laws
A.(B+C)=A.B+A.C
A.B+A.C=A.(B+C)
Rule 1 A  0  A
Rule 2 A  1  1
Rule 3 A.0  0
Rule 4 A.1  A
Rule 5 A  A  A
Rule 6
Rule 7
A  A 1
A.A  A
Rule 8
A.A  0
Rule 9 A  A
Rule 10 A  A.B  A
Rule 11 A  A.B  A  B
Rule 12 A  BA  C   A  B.C
DEMORGAN' S THEOREMS
X.Y  X  Y
X  Y  X.Y
DET: Electronics: Analogue & Digital Electronics (Advanced Higher)
64