TIME BASED ENCRYPTION ON
NETWORK PROCESSOR
TEAM WOLFDALE
The University of Southern California
1
Team Wolfdale Members
Instructor: Dr. Young Cho
Mentor : Siddharth Bhargav
Team Members
Praveen Francis
Gaurav Yadav
Samitsubhro Banerji
Kaushik Raju
2
The Project
A Time Based Content Encryption
Algorithm Based On a Specific
Sender-Receiver IP Pairs.
3
The problems
Encryption at software
level is slow as compared to
hardware level
Most encryption algorithms
use static keys.
HERE we Use a DYNAMIC KEY
4
The General Concept
12.0.1.3
Data
10.0.1.3
SENDER/RECEIVER IP
NO MATCH
Data
10.0.1.3 / 12.0.1.3
10.0.1.3 / 12.0.2.3
10.0.2.3
12.0.2.3
5
The General Concept
12.0.1.3
Data
10.0.1.3
SENDER/RECEIVER IP
Encrypting…
MATCH
SENDER/RECEIVER IP
Decrypting…
MATCH
Encrypted
Data
Data
10.0.1.3 / 12.0.1.3
10.0.1.3 / 12.0.2.3
10.0.2.3
12.0.2.3
6
System Flow Chart
No
Packet
IP Matcher
Unmodified
Packet
Yes
Source
Destination
Timestamp
Processor 1
Payload
Encrypt/
Decrypt
Processor 2
Modified
Packet
7
Multi-threading with branch
ID Stage
MUX
IF Stage
1
PC
PC
PC
PC
0
ADD
Control
Unit
Instruction
Memory Branch
4K
200
300
BS
BNS
BS
BNS
Rs_data(31:0)
Reg File
32*8B
10
Taken
LUT4
101
1
100
Mod4
Counter
Rt_data(11:0)
Rs_data(1)
Rs_data(0)
Rt_data(31:0)
50
BS = Branch if set
BNS = Branch if not set
8
IP Matcher
4 Unit Comparator Block
64 bit
IP
Packet
64-bit
64-bit
If Found
Else
64-bit
64-bit
Processor
and
Timestamp
Register
Source
Destination
Timestamp
Data
Out a
Payload
No
Match
Match
Data
In
Data
Out a
Memory
Bank 1
Memory
Bank 0
Data
Out b
Data
Out b
9
ENCRYPTER/DECRYPTER
Timestamp from
Header
EN1
DATA_IN
Timestamp Reg
EN2
Table of Keys
DATA_IN
E
N
C
R
Y
P
T
D
E
C
R
Y
P
T
DATA_OUT
DATA_OUT
10
Multi-core Implementation
MATCH!!
DONE!!
IP
Matcher
Encrypt /
Decrypt
IP
Matcher
Encrypt /
Decrypt
NO
MATCH!!
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
MAC
IDs
OUTPUT QUEUES
Arbiter
IN FIFO
PF
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
Calculating
Comparing
Encrypt
MAC
checksum..
MAC
data!
ID..
IDs
11
Future Scope Of Work
 Use of sophisticated
encryption/decryption
techniques.
 Implementation of bloom
filter for ip matcher
 Two dummy threads to be
used for additional
network functionalities.
12
Evaluation of Project
 Evaluation Methods
 Secure transmission of data in
between nodes
 Throughput measurement
 Project Results evaluation




logic functionality Check
Bug Analysis
Rectify Design
Compare With The Software
Emulation Results
13
PROGRESS REPORT
Phase
Description
Date
Status
Single Core Processor
with Multi Threading
04/23/2013
Completed
Hardware Accelerators
Design Simulation
04/23/2013
Completed
Multi Core Processor
with Multithreading
04/30/2013
In Progress
Hardware Accelerators
Individual Implementation
05/02/2013
In Progress
Integration of Hardware
Accelerators with Multicore
Processors
05/07/2013
Pending
05/10/2013
Pending
Evaluation of the
System
14
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