Leadless Devices
4 QFN Challenges that will Make you
Scream!
BEST Inc. www.solder.net
info@solder.net
Bottom Terminated Components
The 4 “Biggies”
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Void Reduction
Cleaning
Inspection
Rework
1. Void Reduction
Achieve Reliable Assembly with
Minimal Voiding
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Large area in thermal ground, lots of volume of flux, lots of outgassing
Voiding impedes thermal transfer, reducing the efficiency and lifetime
of the package
No single approach has proven to be the solution
Important to reduce overall % voids and size of largest void
Try combinations of proven approaches to achieve the best possible
process
Solder paste is ~50% flux by volume
• Large paste deposit contains volatiles
• During reflow volatiles must escape to accomplish complete
coalescence
• Low standoff leaves no exit for excess volatiles
Strategies to Reduce Voiding
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Thermal pad and via design
Stencil design
Reflow profile optimization
Thermal Pad Design Considerations
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Strategy: break up thermal pad to discourage
large voids and facilitate venting
“Window paning” creates pathways to vent
volatiles
Reduced pockets of volatiles cause smaller
voids and less overall voiding
Downside: Vent channels result in less solder
joint continuity
Split Thermal Pads
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Split thermal pads reduce the size of voids, but
do not significantly reduce the total voiding area
For thermal transfer, large voids are more
disruptive -> smaller voids allow for more
transfer
Solder mask defined pads offer further
improvement
Dr. Lee et al. study this in “The Effect of
Thermal Pad Patterning on QFN Voiding”
Dr. Lee et al. study this in “The Effect of Thermal Pad Patterning on QFN
Voiding”
Voiding in QFN
Unfilled Via-in-pad
This is why you must “seal” via-in-pad !
Voiding + Via in Pad
• Voiding even with Pad window Paning!
• Excessive voids can also cause co-planarity issues
and open QFN joints
• IPC & JEDEC stipulates at least 50% coverage
criteria for the thermal pad.
Stencil Design
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Instead of printing one large square at the center of QFNs:
 With greater paste volume, voiding increases, so aperture designs
that limit paste volume will reduce voiding
 Break up this square into smaller apertures
 Spaces between printed areas leave paths for volatiles to escape
“Influence of Reflow Profile and Pb-free Solder Paste in Minimizing Voids for QFN
Assembly” by T. Jensen, E. Briggs et al.
Effects of Window Paning
W Coleman; “Printing and Assembly Challenges for QFN Devices”; SMT Magazine, 4/11
Voiding vs. Stencil Thickness
Songninluck, et al; “QUAD FLAT NO LEAD (QFN) PACKAGE PROCESSING IN HIGH THERMAL MASS ASSEMBLY”; SMTAI-10
Voiding vs. Window Pane
“Focal Dot”
8mil spacing
Songninluck, et al; “QUAD FLAT NO LEAD (QFN) PACKAGE PROCESSING IN HIGH THERMAL MASS ASSEMBLY”; SMTAI-10
Reflow Profiling
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There is no “magic” reflow profile to minimize
voiding
For each assembly, the best profile will balance
several requirements:
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Thermal requirements of assembly
Optimal profile for the chosen solder paste
Requirements of other components (ie BGAs)
There will be an optimal profile, it may or may
not minimize voiding
Profiling must be considered but not a solution
2. Cleaning Underneath BTCs
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Low clearance
Large center pad
 High paste/flux volume
 Difficult cleaning flow path
BTC: No-Clean Residue Issues
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No-Clean: Solvents can’t escape =>
residue not safe (even though full
time/temp exposure)
Flux volatilization is a critical factor with
regard to the complexity of the flux
residue so that it becomes benign
The fluxes are not benign until
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they have seen enough heat to volatilize the
solvents
create the insulative residue
this can only be done with enough heat and
removal of the flux carrier
Courtesy of Foresite Inc
BTC No-Clean Residue Issue
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In a no-clean process, when the flux
is activated and fully volatilizes, it
leaves a benign residue with no
impact on field performance.
But when this solvent is not allowed
to release:
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Flux residue is conductive and moisture
absorbing.
Product in the field for 9 months to still
have gooey conductive flux causing
performance problems.
BTC: No-Clean Residue Issues
T Munson; “ELECTRICAL LEAKAGE FAILURES DUE TO ENTRAPPED FLUX BELOW A QFN PACKAGE”; SMTAI-06
BTC Cleaning
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Need to have enough standoff
distance (min’m 2.5mils)
Need to have pathways for the
cleaning solutions to get enough
impingement energy to the “soils”
Need to have enough kinetic energy
to break soils free
Measure using ion chromatography
BTC Cleaning Study
Courtesy Zestron
3. Inspection
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AOI: Pretty worthless
Manual: Depends on wettable surface
Endoscope (edge viewing optical
microscope) reasonable for edge joints
X-Ray: good for voiding, bridges,
wetting only method for central pad
IPC Inspection Criteria
Pullback vs. No-pullback
V Solberg; “ PCB Design Principles for QFN and Other Bottom Termination Components”; APEX-11
Metallization-easier inspection
Shadowing; Solder Balls
Multiple pads different AOI
Algorithms
More Defects; CT Scan
Bastin & Krastev; “QFN PROCESS CONTROL VIA 2D AND 3D CT X-RAY INSPECTION TECHNIQUES “; SMTAI-11
4. Rework
High Yield, Simple and Fast
IPC 7711 3.11
Rework Technique
IPC 7711 3.11
Rework Technique
IPC 7711 3.11
Part Bumping Using a Polyimide
Peel-n-Stick Stencil(s)
IPC 7711 5.8.1.2.
Step #1
Align and apply
stencil to
device. Roll
solder paste
through
apertures.
Part Bumping Using a Polyimide
Peel-n-Stick Stencil(s)
Step #2
Reflow per solder
mfr’s profile
recommendations
Part Bumping Using a Polyimide
Peel-n-Stick Stencil(s)
Step #3
Remove
stencil and
clean.
Surface now
is “bumped”
Part Bumping Using a Polyimide
Peel-n-Stick Stencil(s)
Inspection of “bumped” device
Part Bumping Using a Polyimide
Peel-n-Stick Stencil(s)
Step #4
Prep land
area on PCB
where device
is to be
placed
Part Bumping Using a Polyimide
Peel-n-Stick Stencil(s)
Step #5
Align and
adhere board
stencil on
PCB. Roll
solder paste
into apertures
and clean off
residue.
Part Bumping Using a Polyimide
Peel-n-Stick Stencil(s)
Step #6
Place
“bumped”
QFN into
stencil
apertures.
Feel the
“bumps” fit
into the
apertures
Part Bumping Using a Polyimide
Peel-n-Stick Stencil(s)
Step #7
Reflow as per
solder paste
manufacturers’
profile
recommendations.
Perform visual
inspection.
Perform X-ray
inspection.
Print Quality
Print Reliability
BEST Inc.
bwet@solder.net
www.solder.net