Barrier Layers for Copper ULSI metallization

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AMC2000
Barrier Layers Technology
Prof. Yosi Shacham-Diamand
Department of Physical Electronics
Tel-Aviv University,
Tel-Aviv 69978 ISRAEL
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Outline
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Introduction
Copper Interconnect technology
Barrier layers - overview
Process development and integration
Barrier layers modeling
Barrier analysis, testing & monitoring
Summary
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Introduction
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Structure of Microchips
ULSI metallization technology
Metallization roadmap
Downscaling issues
 Performance
issues
 Manufacturing issues
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Where is the bottom ?
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Copper multi-level metallization
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IBM CMOS 7S process
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Copper chips...
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IBM power PC 750
Mitsubishi Electric eRAMTM family
AMD K7(Athalon)
UMC 0.18 mm process
Motorola 333MHz SRAM
Lucent & Chartered 0.16 mm process
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IBM PowerPC 750
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Structure of microchips
Interconnect network - 6-7 layers of
metallization
Active devices layer ( 1-2 mm)
Silicon substrate (600-800 mm)
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ULSI metallization technology
‫אינטל‬
20009
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Gate and Interconnect delays
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Delay modeling - the barrier effect
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The specific resistance (rb ) of the barrier
layers is higher than that of the Cu, (rCu)
W
H
Without barrier:
L: line length
R w/o  ρCu  L
WH
With barrier (tb: barrier thickness)
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RW
(W 2t b )(H 2t b )
1  2t b (H  W2t b )

L
ρB
L
Cu
 ρ1 
Assumption:
complete barrier coating
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Cu Damascene interconnect resistivity
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Effect of the barrier layer on the interconnect delay
Interconnect delay Tint ~ Rint*Cint - including the barrier.
In the case of a Damascene technology:
Tint
Tint, w/o barrier
rb
rCu

1

( H tb )(W  2 tb )  rb

1 
WH
 rCu 
For rb >> rCu we get the the interconnect delay
increases as the ratio between the actual copper
line cross section and the total cross section.
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Barrier layers - overview
Why do we need barriers ?
Requirements from barriers
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Barrier layers for Cu metallization
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Why do we need barrier layers?
 Copper
affects Si properties
 Cu affects SiO2 properties
 Cu affect most insulators properties
 Cu adheres poorly to bottom and side ILD
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Why do we need a top barrier (capping layer)
 Cu
corrodes
 Cu adheres poorly to top ILD
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Requirements from barrier layers
• Step coverage on high aspect ratio
holes and trenches
•Low thin film resistivity
•Adhesion to the ILD
•Adhesion to Cu
•Stable at all process temperatures
•Process compatible to the ILD
•Process compatible to CMP
•Act as a good barrier
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Barrier layers - types
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Sacrificial
Stuffed - impurities in the grain
boundaries
Amorphous - no grain boundaries
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Diffusion barrier - classification of the
candidates for barriers that has been
investigated in the last 15 years
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transition metals
transition metal alloys
transition metal - silicon
transition metal nitrides, oxides, or borides
Miscellaneous: ternary alloys, a-carbon,
etc.
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Summary of barrier layer classification
Transition metals fail as barrier at lower
temperatures than their nitrides
 transition metal silicides fail due to the reaction
of the Si with the Cu. The reaction is most likely
to happen at the grain boundaries
 Amorphous barriers offer very high reaction
temperatures, however, they have very high
specific resistivity
 The barrier properties depend also on the
deposition method.
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Process development
and manufacturing
considerations
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Step coverage issues
Barrier layer
too thick
Barrier layer
too thin
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Coverage issues
Nonuniform sidewall
deposition:
• agglomeration
• Bad coverage at the
bottom corner - can be
amplified if the bottom
corner has some overetch
of the layer below
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The effect of pre-deposition clean on the barrier integrity
Physical process in Ar+ ions
Reactive clean
Problems
• Damage to the barrier
• Damage to the dielectric
• Barrier metal and Cu
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• Sputtering and re-deposition on the sidewalls
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Copper patterning
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Dry etch
 Difficult,
expensive
 Conventional equipment
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Dual Damascene
 Fully
planar, lower cost,
 New technology
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Cu process options
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Electroplating solutions
• Cu ions - Cu sulfate
• Acid - H2 SO4 for pH adjustment
• HCl - Affects Cu surface adsorption;
Halide ad-layer drives Cu growth. It
also acts as a surfactant and stabilizes
grain growth. Cu deposition is driven
by the desorption of the halides.
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Electroplating Based Process
Sequence
Pre-clean
IMP barrier + Copper
25 nm
10-20 nm
Electroplating
CMP
+ 100-200 nm
AMC2000 Low-cost, Hybrid, Robust Fill Solution
Simple,
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Diffusion barrier for Copper (I)
• PVD Ta,TiN, and TaN
Neutrals sputtering
Collimated & Non collimated
Ions sputtering
RF ionized
HCM- Hollow Cathode Magnetron
• CVD of TiN
Iodine or Chlorine based chemistry
• CVD of Ta and TaN (or both)
Bromide based chemistry
• MOCVD of TiN
TDMAT & TDEAT
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PVD barrier technologies
Target
Target
Target
RF
Substrate
Substrate
Substrate
Bias
DC magnetron
sputtering
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Collimated
sputtering
IMP - Ionized
Metal Plasma
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Diffusion barrier comparison, (M. Mossavi et al., IITC 98)
Properties
Ta - IMP
TaN - IMP
TiN - CVD
Resistivity
170 m.cm
250 m.cm
130 m.cm
Stress
+350 MPa
+1500 MPa
-750 MPa
Barrier
performance
6x1016 at/cm3
6x1017 at/cm3
1017 at/cm3
40%/40%
100%/100%
20
1
Sidewall/bottom 20%/40%
coverage
(0.3mm)
CMP selectivity 23
vs. Cu
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Vias with IMP TaN
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Sputtered WxN barrier
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MOCVD TiN
Precursors: Tetrakis-dimethylamino Titanium
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Other Novel barriers
RuO2
r=40-250
m cm
TaSiN,TiSiN
r=200-600
m cm
WBN
r=300-10000 m cm
CoWP
r=20-120
m cm
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Electroless barriers
Surface activation methods
Wet activation (Pd activation)
Dry (Ion beam sputtered
on Si
seed) on SiO2/Si
1. PdCl2 activation
2. Copper on titanium
3. Cobalt on titanium
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Advantage of Electroless barriers
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Conformal
Low cost
Good quality - low r, low stress
can be integrated with electroless copper
Barrier
Cu
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Co(W,P) barrier layer
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Specific resistivity vs. solution composition
1
e
4
9
e
5
log( r)
8
e
5
7
e
5
6
e
5
1
a
s
d
e
p
o
s
i
t
e
d
f
i
l
m
o
2
1
0
0
C
a
n
n
e
a
l
i
n
g
5
e
5
o
3
2
0
0
C
a
n
n
e
a
l
i
n
g
4
e
5
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0
00
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0
50
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1
00
.
1
50
.
2
00
.
2
50
.
3
00
.
3
5
+
+
[
W
i
o
n
]
/
[
C
o]
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Barrier layers modeling
•Diffusion models - kinetics
•Reaction models - thermodynamics
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Equilibrium thermodynamics of diffusion barriers
(C.E. Ramberg et al., Microelectronics Microengineering, 50
(2000) 357-368)
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Cu makes silicides with silicon
Barriers include transition metal+metaloid (Si,B,or N)
Binary Solid
system solution
TM-N
Broad
Crystal
Tendency
structure to aphase
Simple
Poor
Conductivity
TM-Si
TM-B
Narrow
Narrow
Moderate Fair
Complex Good
Variable
Good
Narrow
Complex
Poor
Si-N,
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Very good
Good
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Ternary phase diagrams
•The lack of Ta-Cu compounds yield a broad range of
compositions in equilibrium with Cu.
•Ti-rich compositions are expected to react with Cu
N
N
TiN
TaN
Ti2N
Ta2N
Cu
Ta
Cu Cu Ti Cu Ti
4
4
3
CuTi CuTi2
Ti
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Barrier Analysis & monitoring
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Materials science techniques:
 AES,
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SIMS, RBS, SEM
Electrical characterization:
 I-V
 C-V
& C-t
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Electrical characterization: MOS capacitors
ID:
Sample
Final Structure:
MOS1
Reference capacitors
Al/SiO2/Si
MOS2
Reference capacitor
Barrier/SiO2/Si
Just the barrier
Barrier/Cu/Barrier/SiO2/Si
Copper between
top and bottom
barrier layers
MOS3
Test device
No barrier at all,
Al metallization
Capacitance measurements:
CV: Flat band voltage, interface states
Ct : minority carrier lifetime, surface recombination velocity
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IV &It: metal/insulator
integrity.
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Ideal MOS capacitance-voltage curve.
Solid curve - High f , Dotted curve Low frequencies.
Oxide thickness is 140. NA = 1·1015 cm-3.
1.0
Low frequency
0.8
C/COX
0.6
0.4
High Frequency capacitance
Low Frequency capacitance
High frequency
0.2
Relaxation
0.0
High frequency - fast sweep
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-4
-3
-2
-1
0
1
2
3
4
5
Voltage (Volt)
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Example:
test of CoWP barrier layers
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CV characteristics of MOS capacitor with a. Co(W,P)/Co and
b. Co(W,P)/Cu/Co(W,P)/Co metallization after 300ºC 30 min.
and 520ºC for 2 hours anneal. (A= 3.57·10-4 cm2).
(a)
1.0
1.0
After 300C, 30’
After 520C, 30’
0.6
0.6
0.4
0.4
0.2
0.2
0.0 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6
Voltage (Volts)
After 300C, 30’
After 520C, 30’
0.8
C/Cox
0.8
C/Cox
(b)
0.0
-6 -5 -4 -3 -2 -1 0 1
Voltage (Volts)
2 3 4
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C-t curves of Co(W,P)/Cu/Co(W,P)/Co/SiO2 capacitors annealed at
400C, 500C and 520C. Device area is 3.57·10-4 cm2.
6.0E-12
520C, 2 hours
hours
500C, 30 min
400C, 30 min.
5.8E-12
Capacitance [F]
5.6E-12
5.4E-12
5.2E-12
5.0E-12
4.8E-12
4.6E-12
4.4E-12
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100
150
200
250
300
350
400
450
500
550
600
Ti me (sec)
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Generation lifetime, tg (sec), and Surface
Recombination velocity, So, (cm/sec)
Al/Co
Anneal
tg
conditions (ms)
As-deposited 65
55
300C, 30’
400C, 30’
500C, 30’
520C, 2 hr
600C, 4 hr
CoWP/Co
So
So
tg
(ms)
3.2
74
2.1
1.6
63
0.9
46
1.3
-
CoWP/Cu/CoWP/Co
So
tg
(ms)
58
1.2
62
1.3
52
2
17
0.9
8
1.3
1-2
0.8
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Copper profiles as measured by AES. The sputtering rate was:
12A/min for Co(W,P) on Cu, 25 A/min for Cu, 10A/min for Co(W,P)
on Co, 8A/min for the sputtered Co.
Co(W,P)
Cu
Co(W,P)
Co
SiO2
Si
40
As deposited
Concentration (Arb.)
35
30
520C, 2hr
25
600C, 4hr.
20
15
10
5
0
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30
40
50
60
70
80
90
100 110 120 130 140
Sputtering Time (min)
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Barrier monitoring techniques
X-Ray fluorescence (XRF) thickness and composition (accurate, 5-10 points /
min)
X-Ray reflection:
Thickness
(Most accurate, 2-5 points / min))
Ellipsometry:
Thickness (low accuracy, fast)
Resistivity
Others…….?..?
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X-Ray reflectivity - Sputtered TiN
dBarrier=30.5 nm, r=5.2 gr./cm3
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References
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Shi-Qing Wang, “Diffusion barriers for Cu metallization on Silicon”,
Proceedings of the advanced metallization conference, MRS
publications, San-Diego, 1993.
The proceedings of the Advanced metallization conferences from 1993 to
1999
The proceedings of the Workshop for Advanced Metallization (MAM)
from 1997 and 1999
Papers in various journals such as the Journal of electrochemical society,
Journal Vac. Sci.Tech., J. of Appl. Phys., J. Material research and more.
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Conclusions
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Dominant barriers for Cu technology are Ta
(IMP), TaN (IMP) & TiN (CVD)
There are still problems, especially in high
aspect ratio features
Other barriers are under study (amorphous,
electroless, etc.)
Barrier technology is an enabling technology
for ULSI metallization
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