Application of phase shifters in superconducting
digital circuits
M. Khabipov, D. Balashov, F. Maibaum, A. Zorin
Physikalisch-Technische Bundesanstalt, Bundesallee 100, 38116 Braunschweig,
Germany
V. A. Oboznov, V. V. Bolginov, A.N. Rossolenko and V. V. Ryazanov
Institute of Solid State Physics, Chernogolovka, 142432 Moscow region, Russia
The work was supported by DFG (German Science Foundation) through grant
ZO124/2-1 and the joint grant of DFG and the Russian Foundation of Basic
Researches and grants of the Russian Academy of Sciences.
Physikalisch-Technische Bundesanstalt, Braunschweig
October 11-16 2009, Chernogolovka
1
Outline
• Introduction
• Basic principles of Rapid Single Flux Quantum (SFQ) circuits
• SFQ circuits fabrication technology at PTB
• Operation of an SFQ circuits with integrated phase shifters
based on
– superconducting loop with trapped flux quantum
– Superconductor-Ferromagnetic-Superconductor p-junction
• Conclusion
• Outlook
October 11-16 2009, Chernogolovka
2
RSJ model of Josephson tunnel junction
V
JJ
R
damping resistor
C
JJ - Josephson junction
I
C – self-capacitance
2
w
2p
ICR2C= c2
Stewart-McCumber parameter c =
wp
F0
Underdamped JJ
I
Ic
Overdamped JJ
I
Ic
IReturn
<V>
0
IReturn
C  1
C >> 1
0
October 11-16 2009, Chernogolovka
<V>
3
Reaction on a short pulse
I(t)
R
I
Ic
“sweep”
of the
dc I-V curve
Idc bias
a few Ohm
a short trigger pulse
Generation of
Result:
a SFQ pulse
(strictly 2p-leap of phase!)
<V>
V(t)

 V(t)dt = F
0

time
This pulse (carrier of information) can be used as a trigger pulse
for other junctions - the basis of Rapid Single Flux Quantum circuits!
(Likharev et al. 1985)
Advantages of RSFQ: quantized information, fast (typically, few ps)
switching time, low level of dissipation
October 11-16 2009, Chernogolovka
4
SFQ pulse generation  move to the
adjacent minimum
U(j) = - EJcosj - (F0/2p) j I +const
R

effect of the trigger pulse!
large damping due to
external shunt resistor
washboard potential
Low amplitude signals (noise)
not reproduced by the circuit
a noise discriminator
2p
j
October 11-16 2009, Chernogolovka
5
Definition of coding in RSFQ logic
clock pulses
V/Vc
V/Vc
V/Vc
„0“
„1“
„0“
information pulse
„0“
„0“
„1“
information pulse
Time, a. u.
The binary code:
presence (absence) of SFQ pulse between adjacent clock SFQ pulses
(for comparison)
different voltage levels (CMOS, TTL, “latching” logic)
October 11-16 2009, Chernogolovka
6
RSFQ dc/SFQ and SFQ/dc converter
circuit
Circuit provide generation and back conversion of SFQ pulses into
voltage signals
I _b
I _in
Li n
J 19
J2
L2
I _L
J1
J3
J4
J5
J17
J 18
L1
J 20
J21
J23
J22
R
J 24
dc/SFQ
converter
Josephson
transmission line
V_out
T-Flipflop with SFQ/dc
converter
V. Kaplunenko et al. IEEE Trans. Magnetics 25, 861-864, 1989
K. Likharev and V. Semenov IEEE Trans. Appl. Supercond. 1, 3-28, 1991
October 11-16 2009, Chernogolovka
7
RSFQ T-flip-flop circuit
Circuit provides a frequency division of SFQ pulses
Ibias

jc = 100 A/cm2
As result
frequency
division !
operation frequency f = Vc /Ф0 =Ic Rn /Ф0 up to 40 GHz
power consumption P = V  Ibias = 15 nW
K. Likharev and V. Semenov IEEE Trans. Appl. Supercond., 1, 1991
October 11-16 2009, Chernogolovka
8
T-flip-flop circuit, results of simulation
Phase drop, input junction
Phase drop, TFF junctions
Voltage, input junction
Voltage, TFF junction
Voltage, TFF junction
October 11-16 2009, Chernogolovka
9
Frequency division realised in CMOS logic
(for comparison)
Paul Horowitz, Winfield Hill. The Art of Electronics,
Cambridge University Press, Second Edition, 1989
Pdyn = CeffV2DD x f
For example, at 30fF/gate at 100MHz and
VDD = 5 V, 75 μW is dissipated per gate
UMBC, University in Mariland, Advanced VLSI design
http://www.csee.umbc.edu
.
The circuit consists of 10 gates and
includes about 50 transistors
October 11-16 2009, Chernogolovka
10
SFQ circuits Nb/Al thin-films fabrication technology
established at PTB
-deposition and etching of
The Nb ground plane
Shielding of an electromagnetic noise,
realization of the low value inductances
- anodization of the ground plane
- deposition of the SiO2 isolation layer
- deposition and etching of the
Cr/Pt/Cr resistor trilayer
- deposition of the SiO2 isolation layer
- etching of the contact holes
realization of the shunt and
bias current resistors
-deposition of the Nb/AlxOy/Nb trilayer
-deposition of a thin SiO2 layer
jc between 100 A/cm2 and 1 kA/cm2
October 11-16 2009, Chernogolovka
11
SFQ circuits Nb/Al thin-films fabrication technology
established at PTB
JJ
-etching of the thin SiO2 isolation layer
and the Nb counter electrode,
definition of JJs
Smallest junction area A=10 µm2
SiO2 -anodization mask
Al2O3
Nb2O5
-anodization with the thin SiO2 layer
as a mask
-etching of the base electrode
SiO2
October 11-16 2009, Chernogolovka
-deposition and etching of the SiO2
isolation layer
12
Cross-section of shunted Josephson
junction in Nb/Al technology
JJ
Nb
Tunnel barrier AlxOy
Al2 O3
Al
Cr/Pt/Cr damping resistor
Rsq=2Ω/sq.
Cr/Pt/Cr
}
Nb2 O5
Thermally oxidized
silicon substrate
SiO2
IV curve of the underdamped JJ
A = 24 µm2
Ic  20 µA
Rn  59 Ω
IV curve of the overdamped JJ
C>>1
Rsh
IR IC
T = 4.2 K
Current I (20µA/div)
October 11-16 2009, Chernogolovka
JJ 
Voltage V (100µV/div)

Voltage V (1mV/div)
Si
A = 24 µm2
Ic  24 µA
Rsh  4 Ω
C ~ 1
IC
T = 4.2 K
Current I (20µA/div)
13
Why we need phase shifting elements in RSFQ?
Qubit control and read out: low back action on Josephson qubit
cells (low value Ic, large value of shunt resistor, low power
consumption)
Low Ic value due to Ic x L ~Ф0 result in proportionally increased
value of inductances L, circuits have a large area and became
sensitive to an electromagnetic noise
Physikalisch-Technische Bundesanstalt, Braunschweig
October 11-16 2009, Chernogolovka
14
Conventional TFF with large storing inductance
Symmetry of the TFF states is due to phase drop
of about p created by dc control current:
Icontr
L
j = p
Compact phase shifters are required
SFS
p-JJ
L
F0
Superconducting loop with
trapped flux quanta
TFF with RC shunted Josephson junctions. Parameters: jc=100 A/cm2, Ic= 16µA, L=130 pH
The p shift can also be realized on the basis of HTS junctions exhibiting the d-wave symmetry
of the order parameter (see T. Ortlepp et al. Science 312, 1495, 2006)
October 11-16 2009, Chernogolovka
15
Superconducting loop with trapped flux quantum as
a phase shifting element
The work carried out in collaboration with the group in TU Ilmenau
f = 
I shifter
I shifter
T = 10 K
External flux F applied at T > TC Nb
(T = 10 K)
Ftrapped = n  F0
T = 4.2 K
External flux F turned of when T < TC Nb (liquid
helium temperature T = 4.2K). Quantized flux
trapped Ftrapped = n  F0
F0  2.07 mVps (single flux quantum)
Flux quantization law
It was proposed as a phase-bias circuit for the Josephson qubit in J.B. Majer et al. APL 80, 3638, 2002.
October 11-16 2009, Chernogolovka
16
Superconducting loop with trapped flux quantum as
a phase shifting element
The work carried out in collaboration with the group in TU Ilmenau
Pinning a flux quanta into ground plane hole
During the cooldown, the flux is
trapped in the ground plane hole.
October 11-16 2009, Chernogolovka
17
Conventional TFF and TFF with
integrated π – shifter
Schematic diagram of the
ordinary TFF circuit
Schematic diagram of the TFF
with integrated p-shifter
TFF input
TFF input
J2
J1
TFF out1
Lint
J3
TFF out2
J1
J2
TFF out1
TFF out2
Lshifter
J4
J3
J4
The large quantizing inductance Lint can be replaced by passive
π – shifter, ensuring bistable functioning of the TFF
D. Balashov et al., IEEE Trans. Appl. Supercond. 17, 142, 2007
October 11-16 2009, Chernogolovka
18
Simpler circuit:
dc-interferometer with integrated π–shifter
dc-interferometer with
integrated π – shifter
Microphotograph of the sample
Ibias
Ibias
Vout
Vout
p-shifter
Isweep
Isweep
JJ
f
JJ
Isweep
Isweep
f+p
J1
J2
Control line
Circuit parameters:
IC  270 µA, RN  0.8 , Lshifter  7 pH (at T=4.2K), and Lshifter  15 pH (at T=10K),
Flux bias current for single F0 operation mode  Icontr  200 µA
October 11-16 2009, Chernogolovka
19
Experimental testing of the
dc-interferometer with integrated π–shifter
Voltage-flux characteristics of the dc-interferometer with
integrated shifter loop realized in jC=1 kA/cm2 Nb/Al technology
J1
V (20 µV/div)
Isweep
Vout
Isweep
J2
1 F0 trapped in the shifter loop
Icontr  200 µA

Ibias
F0

No flux trapped in the shifter loop
Icontr  0 µA
F0/2
Flux  Current Isweep ( 200 µA/div)
Voltage-flux characteristics
October 11-16 2009, Chernogolovka
20
TFF circuit with integrated π–shifter
Microphotograph of the sample
Schematic diagram of the TFF with
integrated p-shifter
TFF input
TFF separate bias
TFF input
p-shifter
J2
J1
TFF out-1
TFF out-1
f
f+p
TFF out-2
TFF out-2
Lshifter
J3
J4
Control line
October 11-16 2009, Chernogolovka
21
Block-diagram of tested circuit including
TFF with integrated π – shifter
p-shifter
I_in
(Divider 2:1)
f
f+p
(Divider 2:1)
V_out2
V_out1
Control line
TFF with p-shifter should operate as a frequency divider 2:1
October 11-16 2009, Chernogolovka
22
Experimental testing of the circuit with integrated
π–shifter
Circuit realized in Nb/Al technology with
jC=1k A/cm2
Voltage (200 µV/div)
When F0 trapped in the
π – shifter loop fout1 = fout2= fin/4

Bias current margin of the circuit is  20%
Current (500 µA/div)

When no flux trapped in the
π – shifter loop fout1 = fout2= fin/2
I_in
V_out1
V_out2
I_in
V_out1
Bias current margin of the circuit is  17%
V_out2
Time t ( 5 ms/div)
October 11-16 2009, Chernogolovka
23
p-junction as a phase inverting element
Josephson current-phase π-junction currentrelation
phase relation
I
I
2p
2p j
j
0


p-JJ
I=Icsinj
I=Icsin[p+j]= -Icsin j
E
E
-p
Symbolic
notation
p
0-junction
energy minimum at 0
j
-p
p
j
p-junction
energy minimum at p
October 11-16 2009, Chernogolovka

E= EJ[1-cosj]
E= EJ[1-cos(p+j )]=EJ[1+cosj]
Bulaevsky, Kuzii and Sobyanin,
JETP Lett. (1977)
24
Superconductor-Ferromagnet-Superconductor (SFS)
junction: 0-state and π–state
Nb-Cu0.47Ni0.53-Nb
p-junction
dF = 12-22 nm
“0”-state
I=Icsinj
“0”-state
“p”- state I=Icsinj
I = Icsin(j+p) = - Icsin(j)
V. A. Oboznov et al. PRL 96, 197003, 2006
October 11-16 2009, Chernogolovka
25
Cross-section of shunted Josephson junction in Nb/Al
technology and ferromagnetic based junction
SIS-junction
jc=100 A/cm2
A = 10 µm2
SFS-junction
jc=850 A/cm2
A = 8x8 µm2
Topologically, the SFS junction is placed between Nb-wiring nodes of pre-fabricated circuit.
October 11-16 2009, Chernogolovka
26
dc-interferometer with integrated SFS
π-junction
Voltage-flux characteristics of the dc interferometers:
a) conventional, b) with SFS p-junction
October 11-16 2009, Chernogolovka
27
Integration of the p- SFS junction into TFF circuit
TFF with integrated π-SFS
junction
Conventional TFF circuit
JTL
JTL
In
JJ
JTL
Out1
JJ
JJ
∆j =
π
L
In
JJ
I_b
JJ
I_b
π-SFS
JTL
JJ
Out2
JTL
JJ
JJ
Out1
JTL
Out2
Proposed in: A. Ustinov and V. Kaplunenko J. Appl. Phys. 94, 5405, 2003
October 11-16 2009, Chernogolovka
28
Integration of the p- SFS junction into TFF circuit
Phase drop, input junction
Phase drop, TFF junctions
Voltage, TFF junction
Voltage, TFF junction
Voltage, p-junction
operation ranges: jc =  32%, Ib =  40%, L =  50% p- junction substituted
by fixed phase shift of p and junction having Ic of large value
October 11-16 2009, Chernogolovka
29
Microphotograph of integrated circuit
V_out1
V_out2
SFS p-junction
JTL
SFQ/dc
JTL
SFQ/dc
TFF
dc/SFQ
I_bias
I_in
50 µm
SFQ pulses generated by dc/SFQ converter, processed by TFF with integrated p-SFS
junction and converted to the voltage levels by SFQ/dc converter circuits
October 11-16 2009, Chernogolovka
30
TFF circuit with integrated SFS π–junction
a) Block diagram of the test circuit
October 11-16 2009, Chernogolovka
b) microphotograph of the TFF circuit
31
Proof of correct operation of TFF circuit with
integrated SFS π–junction
Circuit realized in Nb/Al technology with jC=100 A/cm2
SF S p - junc tion
TFF out1
20 A/div
Iin
TFF -core cell
T in
T o ut1 =T o ut2 =4T in
Vou t1
50 V/div
Vou t2
50 V/div
Input
TFF out2
50 m
Time t, 10 ms/div
When SFS junction is in a π–state then circuit operates properly
Tout1 = Tout2= 4Tin
Bias current margin of the circuit is  19% and limited by bias current margins of
dc/SFQ converters!
October 11-16 2009, Chernogolovka
32
Conclusion
• We have successfully integrated the phase shifting elements in RSFQ
circuits without deep modification of currently available technological
process.
• The following phase shifting elements were experimentally studied:
– superconducting ring with trapped
flux quantum
– SFS p-junctions
October 11-16 2009, Chernogolovka
F0
p-JJ
33
Outlook
Measurements of operation ranges of bias current of SFQ circuits
with integrated SFS p-junctions
- design of the TFF circuit with separate bias current
Bit error rate (BER) measurements
- realisation of the TFF circuit incorporated into ring
oscillator
October 11-16 2009, Chernogolovka
34
Integration of the p- SFS junction into TFF circuit
Schematic for the circuit simulation, operation ranges, jc =  32%, Ib =  40%, L =  50%
p- junction substituted by fixed phase shift of p and junction having Ic of large value
October 11-16 2009, Chernogolovka
35