Status of CMS CSC upgrade in LS1
Present CSC Status
ME 4/2 project
ME 1/1 project
4/8/2015
Petr Levchenko
NEC 2013, Varna
1
CSC Upgrade
4/8/2015
Petr Levchenko
NEC 2013, Varna
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Total weight : 12,500 t
Overall diameter : 15 m
Overall length : 21.6 m
Magnetic field : 4 Tesla
6 layer multi-wire
proportional chambers
MUON
ENDCAPS
Cathode Strip
Chambers
Resistive Plate Chambers
4/8/2015
Petr Levchenko
NEC 2013, Varna
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Main goals of CSC Upgrade
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Build , install and commossion72 ME4/2
chambers to complete the 4th station. For the
moment YE3 disk uncompleted due to missing
outer (1.2<η<1.8) ME4/2
Remove, refurbish, reinstall and commission
72 ME1/1 chambers (1.6<|h|<2.4)
Introduce into the DAQ optical readout
electronics and increase number of readout
channels (SLink)
Largely extent the LV and HV systems
4/8/2015
Petr Levchenko
NEC 2013, Varna
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Present Status (Sep 04-Oct 11)
Schedule driven by YE+4 disk construction with all other activities
requiring crane in the shadow (ME1/1 PP)
4/8/2015
Petr Levchenko
NEC 2013, Varna
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Recent CMS View
4/8/2015
Petr Levchenko
NEC 2013, Varna
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Chamber production workflow
Incoming parts
Kit preparation
Panel bar gluing
Wire wiring, gluing, soldering (Lab 1)
Electrical components hand soldering
20m
platform
•
Chamber assembly & test (Lab 2)
Long term gas, HV tests
Electronics assembly & Fast site
test
Final inspection packing, storing
10m
10m
Strip gluing
Gas
Electronics
assembly
clean Lab 2
15m
4/8/2015
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•
•
25m
Long term gas &
HV
Chamber rack
5m
panel storage
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•
•
•
•
Petr Levchenko
Fast site testing
hand soldering
10m
Chamber
storage
area
6m
Packing
7m
Panel cleaning/gluing
clean Lab 1
10m
NEC 2013, Varna
Loading
area
6m
Incoming
parts
7m
Kit
preparatio
n
15m
7
wire winding
FR4 bar
bonding
chamber
assembly
Wire pitch and tension
HV testing
chamber
integration
4/8/2015
chamber testing
Petr Levchenko
NEC 2013, Varna
wire soldering
components
soldering
chamber
installation
8
ME4/2 schedule
(original plan)
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Production schedule
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A production rate of 1 chamber/week (7 working days) is our target
1st endcap
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By February/March 2013 we hope to have built 31 chambers (5 already
on YE+3 disk, 2 more ready and 6 in the workflow at b904).
The additional 36 chambers will be ready by March of 2014.
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
2nd endcap
Note: plan to re-use on-chamber electronics from ME1/1
Our aim is to complete the project on time for installation during LS1,
assuming schedule for LS1 will not slip (starting on Nov 17).
4/8/2015
Petr Levchenko
NEC 2013, Varna
9
Achieved chamber
production
1st endcap
(30 chambers)
Xmas
break
Not considering time for chamber long term HV training (8 weeks),
electronics integration (2 days) and final testing (3-4 days)
assuming a
rate of 3.3
CSC/month
4/8/2015
Petr Levchenko
NEC 2013, Varna
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Chamber production chart 2nd
endcap
(36 chambers)
ME4/2 chamber factory status: 89% of chambers now assembled
Rate = 4
CSC/month
4/8/2015
Petr Levchenko
NEC 2013, Varna
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ME4/2 Electronics Update
RAT aux card (behind)
Trig Motherboard
Clock Control Board
DDU Board
DAQ Motherboard
Slow Control
Muon Sector Receiver
Lev-1 Trigger
Trigger-Timing-Control
D T D T D T D T D T C MT D T D T D T D
MM M MM MM M M M C P M MM M M MM M
CBB B BB BBB BB BCB BB BB BB B
O
N
T
R
O
L
L
E
R
Peripheral Crate
on iron disk
CFEB CFEB CFEB CFEB CFEB
LV Distribution
Board
System Layout
4/8/2015
Petr Levchenko
Readout Data
LVDB
ALCT
CSC
FED Crate in USC55
Cathode Front-end Board
Anode LCT Board
Anode Front-end Board
NEC 2013, Varna
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CSC ME4/2 project final remarks
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The ME4/2 on-chamber and DAQ electronics
partially come from the ME1/1 system after
refurbishment
All board stay unchanged except (UCLA- J.
Hauser) ALCT mezzanine boards
Small Spartan-6 FPGA cards
 Radiation tested, 100% compatible firmware,
passes STEP testing
 Originally for ME4/2 only, but low cost 
replace on ME1/1 as well
LV system enriched by four Maraton power
supplies and LV delivery system (Junction Box)
partially recuperated from ME1/1 system
HV system now is the paste copy of station 2.3
with power capacity to supply 72 chambers
4/8/2015
Petr Levchenko
NEC 2013, Varna
Spartan-6 vs Virtex-E
features:
• 10x logic
• 2x speed
• Low power ~same
• SEU mitigation options
• TMB-compatible
13
ME1/1 Refurbishment and Testing of Boards
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All ME-1/1 Chambers have
been removed from the Muon
Endcap and taken to the SX5
area at the CMS Center
17 chambers have been
refurbished and two have been
installed on +YE1 disk
The old electronics already
used for the ME-4/2 system
Each refurbished chamber
undergoes STEP tests with
upgraded readout electronics
ME-1/1


4/8/2015
Petr Levchenko
ME1/1 SX5 area
LTT
NEC 2013, Varna
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ME1/1 electronics
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Many new items
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Electronics designs are fully
validated
DCFEB, ALCT S6, LVDB7,
LVMB7 and PPIB production is
complete
>300 of 550 cathode boards
(DCFEB) received at CERN
Off-chamber electronics


OTMB are in production
ODMB design is finished, awaiting
a Production Readiness Review
4/8/2015
Petr Levchenko
NEC 2013, Varna
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ME-1/1 On-Chamber Electronics
Upgrade_1
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Remove triple-strip-ganging in ME1/1a region (57 CFEB)
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ALCT  ALCT(S6): Anode readout board
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Suppress low-pT mis-measured muons
Reduces ambiguities due to combinatorics
FPGA Virtex E  Spartan 6
New, faster FPGA to handle rates
Low Voltage Distribution Board to supply low voltage to on-chamber
electronics and Low Voltage Mezzanine Board is the interface between
the LVDB and the readout board ODMB, which we use for monitoring
and control
Upgraded
Current
CFEB CFEB CFEB CFEB
LVDB
Cathode Front-end Board
ALCT
Anode LCT Board
CSC
CFEB
4/8/2015
Anode Front-end Board
Petr Levchenko
NEC 2013, Varna
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ME-1/1 On-Chamber Electronics
Upgrade_2
Cathode Front End Boards  Digital Cathode Front End Boards (All OSU
design – S.Durkin, B. Bylsma)
•
•
Virtex 1  Virtex 6
Replace the current analog CFEB with SCA and 16:1 multiplexing ADC by digital design
with flash ADC for each channel and digital pipeline storage
CLK,L1A,JTAG...
CLK,L1A,JTAG...
• Optical Data and Trigger Path
TMB Path optical
TMB Path copper
Data Path copper
Data Path optical
Virtex I
Virtex 6
Trig brd2brd
Trig brd2brd
CFEB
Comparator ASIC
DCFEB
Comparator ASIC
6 Wilkinson ADCs
Flash ADCs
Switch Capacitor ASIC
Fully Diff Amps
Buckeye Amp/shaper
ASIC
Buckeye Amp/shaper
ASIC
Coupling/Protection
Coupling/Protection
4/8/2015
Petr Levchenko
NEC 2013, Varna
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Low Voltage Distribution Board (LVDB7)
Terminal block
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RDMS design (V.Y. Karjavin)
Reviewed in February
Fabrication and assembly in Russia
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Fixation of LV cable
PCB fabrication complete
Assembly and test have been completed
72 production boards + spares currently at CERN
4/8/2015
Petr Levchenko
NEC 2013, Varna
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Low Voltage Mezzanine (Monitor) Board
(LVMB7)
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UC Davis design (Ray
Gerhard)
Performs same functions as
previous LVMB but with
increased number of
channels
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Underwent mini (internal)
PRR in May
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interface between ODMB
and LVDB boards
Control and monitoring of
LVDB power channels
Production LVMB7 with skew clear cable

36 assembled production
boards at CERN
One FET replaced for rad
hardness
Buffer added for
temperature monitoring
All PCB’s have been
fabricated
4/8/2015
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Petr Levchenko
NEC 2013, Varna
Patch Panel Interconnect Board (PPIB)
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PPIB: active interface board
in patch panel to take 2 skew
clear cables from OTMB and
distribute signals to 7
DCFEBs
Designed by Mike Matveev
(Rice)
Prototype arrived in April;
production completed and all
board delivered to CERN
2 skew clear
cables to
ODMB
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4/8/2015
Petr Levchenko
7 new cables
to DCFEBs
Uses existing skew clear
cables to connect to ODMB
Uses new cables to connect
PPIB to DCFEBs
NEC 2013, Varna
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ME-1/1 Readout Electronics Upgrade

Optical Trigger Mother Board
(OTMB). UCLA – J. Hauser
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Replaced Mezzanine card. TAMU – J
Gilmor
 Virtex 6 FPGA enhances our
capabilities
 memory & speed for improved
trigger logic
 Use 7 multi-gigabit serial links for
data from DCFEBs
New Base Board
 A new front panel to make room
for optical links
 Modification specifically targets
improvement in power
distribution
 Full backwards compatibility is
maintained
4/8/2015
Petr Levchenko
NEC 2013, Varna
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ME-1/1 Readout Electronics Upgrade
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Optical Data acquisition Mother Board (ODMB) UCSB, NE
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
4/8/2015
Optical Transceivers
New Virtex-6 to handle the fiber optic data and optical
transmission for 7 DCFEBs
Petr Levchenko
NEC 2013, Varna
22
System Test of Endcap Peripheral Crate
and Chamber Electronics (STEP Tests)
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A comprehensive tests of the chambers which can help detect problems with
connectivity, noise, and electronics firmware
Set of tests below are performed on all me-1/1 chambers being refurbished
All CSC chambers installed on the muon endcap have undergone these tests
STEP tests
Slow Control
Anode Front End Board Threshold and Analog Noise test
Anode Front End Board Noise test
Anode Front End Board Time-delay verification
Pipeline Depth test
Digital Cathode Front End Board Noise test
Digital Cathode Front End Board Connectivity test
Digital Cathode Front End Board DAQ-Path Calibration: Pulse Response and Cross Talks
Digital Cathode Front End Board DAQ-Path Calibration: Amplifier Gain
Digital Cathode Front End Board Comparator Thresholds and Analog Noise
Digital Cathode Front End Board Left/right Comparator Logic test
ALCT self-trigger on cosmic test
High-statistics cosmic test
Chamber gain map
4/8/2015
Petr Levchenko
NEC 2013, Varna
23
Some items…
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ME1/1 electronics upgrade invoke deep changes in LV system
LV system enriched by eight Maraton power supplies and LV delivery system (Junction Box) was
completely redesigned by S.Lusin and produced by Wisconsin and now in CERN
In order to prove high reliability new CSC electronics special Low Voltage Test stand (LTT)has been built
in SX5 test area. It has capacity to run six chambers in the same time
* CSC DAQ hardware in USC
- number of readout channels (SLink) increased from 8 to 36 to better cope with higher rates and new
chambers
- chamber grouping modified for better load balancing
* CSC computers
- upgrading to more powerful server PCs for detector control and VME communication
- new interface cards for VME communication
* CSC software
- adapting to the new electronics on the innermost 72 chambers
. configuration
. control and monitoring (+DCS)
. data format
- updating operating system to SLC 6 or 7 (based on Red Hat EL 6 or 7)
- updating to latest CMS online software framework
- expanding the scope of expert system
- exploiting parallel processing
- consolidating applications
4/8/2015
Petr Levchenko
NEC 2013, Varna
24
Installation schedule

Very intense in Oct-Nov for + side endcap:
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ME4/2 starts Oct. 7, want 24/7 operation for commissioning
ME1/1 starts Oct. 17
4/8/2015
Petr Levchenko
NEC 2013, Varna
25
Summary
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CSC Upgrade on it straight way, but still lot of work
to do….

ME4/12 project is close to final stage.

ME1/1 refurbishing goes well.

In spite of some delay CSC installation going to
happened soon
4/8/2015
Petr Levchenko
NEC 2013, Varna
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