Georgia Tech Digital Back-end
µHRG interface
Curtis Mayberry
School of Electrical and Computer Engineering
Georgia Institute of Technology
January 13th, 2014
Contact: Curtisma@gatech.edu
www.ece.gatech.edu/research/integrated-mems/
Topics
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System Design
Digital Processing
ADC
DAC
Power Supply
AFE Interface
Feed Through Cancellation Tuning
Review Measures
Topics
2
System Overview
• Analog Front End (Red Board)
– Device Pad
– Pickoff Channels (Node and Antinode)
– Forcer Channels (node and Antinode)
– Feed-through Cancellation (x4)
– Quadrature Amplifiers (50v)
• Digital Back End (GT BE)
– 24 bit ADC (8 Channels) and LPF ADC Drivers
– 16 bit DAC (8 Channels) and Reconstruction LPF
– Feed Through Cancellation Tuning Digital Potentiometers
• Digital Signal Processor (TI Tiva C Launchpad)
– 80 MHz MCU Development Board
System Design
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System Diagram
System Design
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Microcontroller: TI Tiva C Series
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80 MHz 32bit MCU (internal PLL to adjust)
4xSPI Serial communication
Single Precision Floating point
128 kB Flash
Up to 43 GPIOs
Tiva C Launchpad
– Microcontroller Part Number:
TM4C123GH6PMI
– On-board ICDI
• USB programmer and debugger
– 40 Pin Header to connect to back-end
– On-board RGB LED and 2 Switches
– USB Powered
Digital Processing
Alternative Signal Processor: FPGA
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Spartan 6 XC6SLX9 FPGA
84 digital IO pins
8 analog inputs
8 general purpose LEDs
1 reset button
1 LED to show when the FPGA is correctly
configured
On board voltage regulation that can
handle 4.8V - 12V
A microcontroller (ATmega16U4) used for
configuring the FPGA, USB
communications, and reading the analog
pins
On board flash memory to store the
FPGA configuration file
Digital Processing
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Connection: Launchpad
• Board designed to mate on top
of Tiva C series Launchpad
• Uses female 0.1” Low profile
Headers by Samtec to mate with
the Launchpad
• Can use ribbon cable and header
strip to reposition Launchpad
Interface
Connection: Launchpad Ports
Tiva C Launchpad Pinout
Launch Pad
Pin
3.3V
GND
5.0V
GND
USR_SW2/
WAKE (R1)
RESET
Red LED
Blue LED
Green LED
USR_SW1
Connection Port Con Pin
- J1.01 TEST0
GND
- J2.01 TEST1
- J3.01 CLKDIV
GND
- J3.02 ~SYNC
CLK
GPIO PF0 PF0 J2.04
MODE0
- J2.05 MODE1
R2
PF1
- FORMAT0
R11
PF2 J4.01 FORMAT1
R12
PF3 J4.02 FORMAT2
R13
PF4 J4.10
SCLK
~DRDY/
FSYNC
DOUT1
DOUT2
DOUT3
Need to Remove
DOUT4
PB6-PD0
PB6 J2.07 DOUT5
R9 (0Ω )
PB6-PD0
PD0 J3.03 DOUT6
PB7-PD1
PB7 J2.06 DOUT7
R10 (0Ω )
PB7-PD1
PD1 J3.04 DOUT8
Interface
ADC
DAC
Connection Port Con Pin
~LDAC_FORCER
GPIO PE4 PE4 J1.05
~LDAC_QUAD
GPIO PE5 PE5 J1.06 ~CLR
GPIO PE0 PE0 J2.03
M1PWM5 PF1 J3.10 SCLK
GPIO PA6 PA6 1.09 SDIN
GPIO PA7 PA7 1.10 SDO
GPIO PC4 PC4 J4.04 ~SYNC
GPIO PC5 PC5 J4.05
GPIO PC6 PC6 J4.06
SERIAL
SPI2_CLK
PB4 J1.07
Connection
GPIO P
GPIO P
GPIO P
SERIAL
SPI0_CLK
SPI0_MOSI
SPI0_MISO
SPI0_FS_CS
Port
PE1
PE2
PE3
Con
J3.07
J3.08
J3.09
PA2
PA5
PA4
PA3
J2.10
J1.08
J2.08
J2.09
PD0
PD3
PD1
PD2
J3.03
J3.06
J3.04
J3.05
SPI2_FS_CS PB5 J1.02
SPI2_MISO
GPIO PB0
GPIO PB1
GPIO PB2
GPIO PB3
GPIO PB7
GPIO PD6
GPIO PD7
PB6
PB0
PB1
PB2
PB3
PB7
PD6
PD7
J2.07
J1.03
J1.04
J2.02
J4.03
J2.06
J4.08
J4.09
DPOT
SCLK
DIN
~CS (U9)
~CS (U14)
SERIAL
SPI1_CLK
SPI1_MOSI
DPOT1_CS
DPOT2_CS
Launchpad Interface Pinout
Interface
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ADC: High Resolution
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TI ADS1278
24 bit, up to 111 dB SNR (52kSPS)
8 Channel, simultaneous sample
Up to 144 kSPS (w/ 106 SNR)
SPI or Frame-Sync Serial Interface
No registers: all settings set by pins
(GPIO)
• Power Supplies
– Analog VDD: 5v
– Digital Core: 1.8v
– IO VDD: 3.3v
• Initialization
– Settings set digitally by GPIOs
– Jumpers: Clock input selection
and power down selection
ADC
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ADC Sampling Frequency and Resolution
• Is a 144 kSPS sampling frequency fast
enough?
• Over-sampling Rate
– High-resolution mode: 128
– All other modes: 64
– 39 dB or 45 dB (HR) of image
Rejectioin
• Is 24-bits of resolution good enough?
– 𝐿𝑆𝐵 =
5𝑣
224 −1
= 298 𝑛𝑉
– More than high enough resolution
ADC
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ADC Schematic: Main
Fully Differential
ADC Drivers (4ch)
ADC Shutdown Jumpers
Single Ended
ADC Drivers (4ch)
Clock Input
Selection Jumper
Common Mode Buffer
ADC
Fully Differential ADC Driver
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OPA1632
Fully differential Audio Op-amp
sets common mode for ADC input
LOW NOISE: 1.3nV/√Hz
Gain Bandwidth: 180MHz
Jumper Option: ground Vin- for
single-ended to differential
conversion
• ADC input channels 1-4
– Ch.1: Node Pickoff
– Ch. 2: Antinode Pickoff
– Ch. 3: Ain 3
– Ch.4: RTD
• Supply: ±8v
• Symmetric and Balanced Layout
ADC
Schematic
Layout
AC Simulation Results
AC Response @ fmax = 10 kHz
Gain = 1 (-6 dB for each differential output)
Phase = -3.76o
Corner Frequency: 195.96 kHz
Gain Peaking: 1.07 dB
ADC
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Transient Simulation Results
Outputs
Input
ADC
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ADC Common Mode Voltage Buffer
• Buffers 2.5v Common
Mode Voltage from
ADC
• Op-amp
– OPA350
– Low Noise:
5nV/√Hz
– Unity-gain stable
– Single Supply: 5v
ADC
Schematic
Layout
Voltage Reference
• ADR4525
• 2.5v
• Output Noise (0.1Hz to 10 Hz):
<1μVpp
• Initial Output Voltage Error:
0.02%
• Input Voltage Range: 3v-15v
– (Running off of regulated 5v
Rail)
• Output current:±10mA
• TCVOUT: 2ppm/oc
• Solder Heat Shift: ±0.02%
• Long Term Drift:
25ppm/1000hrs @60oc
ADC
Reference Schematic
Trace to ADC
Length: 17.08 mm
Width: 0.35/0.254mm
Reference Layout
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ADC Layout
Channel Shutdown
Jumpers
CLK Selection
Jumper
CH1
Fully Diff
ADC Driver
ADS1278
ADC
Single-Ended ADC
Drivers
Fully Differential
Channels
5-8 (4ch)
ADC Drivers
CH4
Fully Diff
ADC Driver
ADC
CH3
Fully Diff
ADC
Driver
CH2
Fully Diff
ADC
Driver
DAC: High Resolution
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ADI AD5754
16-bit
4 Channel
Serial clock: up to 30 MHz
Programmable Bipolar/unipolar output
– +5 V, +10 V, +10.8 V, ±5 V, ±10 V,
±10.8 V ( only 5v, ±5 V w/ Vs= ±8 V)
• INL error: ±16 LSB maximum,
• DNL error: ±1 LSB maximum
• Integrated output and reference
buffers
DAC
DAC Reconstruction Filter
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DAC
2nd Order Sallen-Key Filter: Fc = 15kHz
1st Order RC: Fc = 15.915 kHz
Amplitude and Phase:
10kHz: -92o
160kHz: -258o
Op-amp Selection
• OPA 4140:
• 4 channels/package
• Noise: 5.1 nV/Hz
• Input Bias Current: 0.5pA
• Id: 2.0 mA
• Vdd max: ± 18 V
• SOIC-14
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DAC Reconstruction Filter:
AC Simulation Results
DAC
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DAC Resolution, sampling rate, and DR
• Resolution
– 16-bit
– 𝐿𝑆𝐵 =
10𝑉
216 −1
=153 μV
• Sampling Rate
– Max serial clock frequency = 30 MHz
– 24 bit word
– Max Sampling Rate ≈ 30MHz/(30cycles/sample) = 1 MSPS
• DR (due to quantization) = (6.02dB/bit)*16bits = 96 dB
• Alias Rejection: 61.2 dB (assuming 150 kSPS)
DAC
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DAC Main Schematic
Output
Format
Jumper
Quadrature
Grounding
Options
Reconstruction
Filters
DAC: AD5754 Daisychained
DAC
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DAC Layout
Reconstruction
Filters
Quadrature
Grounding
Options
DAC
Output
Format
Jumper
DAC: AD5754 Daisychained
Connection: External and AFE (“Red”
Daughterboard) Interface
• SMA connectors for power and data connections
• Only 7 connectors total (3 SMA Supplies + 4 USB)
Interface
Digital Potentiometers: Feed-through
Cancellation Tuning
• Digital Potentiometers used to
control feedthrough cancellation
gains
• 4 channels total
• 10kΩ maximum resistance per
channel
• Parallel and series resistors allow
adjustment of resistance
• Interface: 1 SPI channel, 2 CS
• Screw terminals to connect to AFE
Feed Through Cancellation Tuning
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Power Supplies: 1.8v, 3.3v, and 5v
• Regulated 1.8v, 3.3v, and 5v supplies
• TPS767D318
– Dual Supply: 3.3v and 1.8v LDO
– Output Current: 1.0A per regulator
– 2% Tolerance
– Power –on reset
• unused – maybe I should add
this to the reset sources?
– Need 3.3v for digital logic
– Need 1.8v for ADC core
• TPS78650
– 5.0v LDO
– 2% Tolerance
– Vin: up to 10v (8v used)
Power Supply
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Layout and Schematic Checks
• Schematic
– ERC: Electrical Rules Check: No Major
Problems
• Layout
– DRC: Design Rules Check No Errors
– LVS: Layout vs. Schematic: No
differences
Review
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DFM Review
Review
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Complete Main Schematic
Review
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3D Visualization
Top
Bottom
Review
Missing 3D Models: 90 degree SMA Connectors, jumper headers
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