OIF Electrical Interfaces
SXI-5 and TFI-5
Tom Palkert
Applied Micro Circuits Corporation (AMCC)
OIF Electrical Specifications
Link Layer
NP
ATM
SAR
System Packet
Interface (SPI)
SERDES Framer
Interface (SFI)
Data
SERDES Framer
Interface (SFI)
Optical
Interface (VSR)
Clock
Status
Data
OR
TDM
Switch
Fabric
Status
Data
Data
Clock
Clock
PHY
Device
FEC
Data
Data
Data
Data
Clock
Clock
TDM Fabric to
Framer Interface (TFI)
SxI
SERDES
Device
and
Optics
Common Electrical Specification
For SFI-5; SPI-5; and TFI-5*
* TFI-5 optimized for backplane applications
SxI-5 Common Electrical Interface
Transmit
Link Layer
Device
Receive
Link Layer
Device
System Packet
Interface (SPI)
SERDES Framer
Interface (SFI)
SERDES Framer
Interface (SFI)
SxI-5
SxI-5
SxI-5
SxI-5
Data
Status
Data
OR
Status
Data
Data
Clock
Clock
PHY
Device
FEC
Data
Data
Data
Data
Clock
Clock
TFI
TDM Fabric to
Framer Interface (TFI)
Optical
Interface
SERDES
Device
and
Optics
SxI-5 Common Electrical Interface
System
TXREFCK
C
to
Optics
TXREFCK
TXDATA [15:0]
TXREFCK
C
D
TXDSC
TXDSC
TXDCK
TXDCK
TXCKSRC
TXCKSRC
B
Framer
D
TXDATA [15:0]
A
RXDATA [15:0]
FEC
Processor
A
B
RXDSC
RXDSC
RXDCK
RXDCK
B
A
B
A
Serdes
RXDATA [15:0]
RXS
RXS
RXREFCK
Optics to System
Deskew signal aligns data channels
RXREFCK
SxI-5 Common Electrical Interface
SERDES Framer
Interface (SFI-5)
System Packet
Interface (SPI-5)
SERDES Framer
Interface (SFI-5)
Transmit
Interface
(SPI-5)
Transmit
Link Layer
Device
Data
Data
Data
Status
Clock
Clock
PHY
Device
Receive
Link Layer
Device
FEC
Device
Data
Data
Data
Status
Clock
Clock
Receive
Interface
(SPI-5)
Provide well defined voltage levels and timing budgets
SERDES
Device
and
Optics
SxI-5 Common Electrical Interface
SERDES Framer
Interface (SFI-5)
System Packet
Interface (SPI-5)
SERDES Framer
Interface (SFI-5)
Transmit
Interface
(SPI-5)
Transmit
Link Layer
Device
Data
Data
Data
Status
Clock
Clock
8"
Receive
Link Layer
Device
PHY
Device
8"
FEC
Device
8"
Data
Data
Data
Status
Clock
Clock
SERDES
Device
and
Optics
Receive
Interface
(SPI-5)
Capable of driving at least 8 inches of FR4 with 1 or 2 connectors
SxI-5 Common Electrical Interface
Ideal
0-crossing
point
Sampling
point
Ideal
1-crossing
point
True
Complement
Jitter : Phase variations in a signal (clock or data).
Total Jitter is composed of both deterministic and random content.
C
D
TXDATA
FEC
Processor
Serdes
RXDATA
B
A
Differential signal amplitude [V]
SxI-5 Common Electrical Interface
YT1
YT2
0
-YT2
-YT1
0
XT1 XT2
1-XT2 1-XT1
Normalized bit time [UI]
The transmit eye mask specifies the jitter at reference
points A and C
1
D
C
TXDATA
FEC
Processor
Serdes
RXDATA
B
A
Differential signal amplitude [V]
SxI-5 Common Electrical Interface
YR1
YR2
0
-YR2
-YR1
0
XR1 XR2
1-XR2 1-XR1
Normalized bit time [UI]
The receive eye mask specifies the jitter at
reference points B and D
1
SxI-5 Common Electrical Interface
Relative Wander
between lanes x
and y
Peak to Peak
Lane Y
Lane X
Skew between
lanes x and y
Wander: The variation in the phase of a signal (clock or data) after
filtering with a low pass filter.
Skew: The constant portion of the difference in the arrival time
between two signals.
TFI-5
TDM Fabric to Framer Interface
Reference Diagram
T
D
M
S
w
i
t
c
h
TFI-5
Mapper
SONET/SDH
framer
TFI-5
Mapper
OTN
framer
TFI-5
Mapper
TFI-5
Mapper
TFI-5 link
10GbE LAN PHY
Framer
10GbE WAN
PHY Framer
OC-3/12/48/192/768
STM-1/4/16/64/256
SONET/SDH
signals
OTU1/2/3
OTN (G.709)
signals
10 GbE LAN PHY
10 GbE WAN PHY
(OC-192/STM-64)
Ethernet
signals
TFI-5 Requirements
 Support SONET/SDH framers with line-side interfaces of OC-48/STM-16, OC-192/STM-64, and OC768/STM-256 and multi-channel framers with lower rate line-side interfaces with an aggregate
bandwidth of N x OC-48/STM-16. (e.g. quad OC-12/STM-4).
 Support G.709 OTN framers and 10GE LAN/WAN PHY framers by mapping into a SONET/SDH
frame
 Uses scrambling to ensure transition density
.
 Support lane bandwidths of 2.488 Gb/s (STS-48) or optionally 3.1104 Gbps (STS-60).
 Support de-skew between TFI-5 lanes originating from multiple framers or fabric devices.
 Support STS-1 Switching fabrics constructed from multiple devices.
 TFI-5 device shall be capable of checking for errors.
 Capable of driving at least 30 inches of PCB with 2 connectors for intra-shelf environments and at
least 100 meters over optics for inter-shelf environments.
 Support DC coupling. AC coupling is optional.
 Provide a clear forward migration path to future fabrication processes.
 Wide availability of components.
TFI-5 Signal Definitions
Signal Name
TFIDATA
Function
The TFI-5 Data (TFIDATA) signal carries the data
between the Framer and the Switch Fabric. The
same signal definition is applicable to data transfer
in the Framer to Fabric direction, and the Fabric to
Framer direction.
TFIREFCK
The TFI-5 Reference Clock (TFIREFCK) signal
provides timing reference to all the TFI-5 data
(TFIDATA) signals in a system.
TFI8KREF
The TFI-5 8kHz Frame Reference (TFI8KREF) signal
provides reference to frame boundaries for all the
devices in a TFI-5 system.
TFI-5 Layered approach
Client signal
Mapping Layer
Connection Layer
Link Layer
TFI-5 Link
TFI-5 System Model detailing extent
of Layers
TFI-5 Mapping Layer
TFI-5 Connection Layer
TFI-5 Link Layer
TFI-5 Link Layer
Switch
Ingress Framer #1
..
..
.
Mapping
of client
signals
STS-1 (x48)
connect.monitoring
STS-1 (x48)
connect.monitoring
STS-1 (x48)
connect.monitoring
STS-1 (x48)
connect.monitoring
Link
framer
Link
framer
Link
framer
Link
framer
TFI-5 Link
Link
framer
Link
framer
Link
framer
Link
framer
Egress Framer #1
Link
framer
Link
framer
Link
framer
Link
framer
TFI-5 Link
Link
framer
Link
framer
Link
framer
Link
framer
STS-1 (x48)
connect.monitoring
STS-1 (x48)
connect.monitoring
STS-1 (x48)
connect.monitoring
STS-1 (x48)
connect.monitoring
Mapping
of client
signals
..
..
.
STS-1
Time Slot
Interchange
Ingress Framer #n
..
..
.
Egress Framer #n
..
..
.
..
..
.
..
..
.
TFI-5 Frame Format
1
2
N
A1
A1
A2
A2
.....
H1
H1
H2
H2
.....
B2
B2
A1
1
3N-1 3N 3N+1
............
A2
B1
3
4
H1
H1
5
B2
B2
H1
B2
H2
H2 H3
H3
H3
.....
H2
.....
CM CM CSI CSI CSI
H3
.....
H3
.....
CSI CSI
6
7
STS-SPE/VC
area
2
..........
N+1 N+2 N+3 N+4 ..... 2N-1 2N 2N+1
..... N-3 N-2 N-1
8
9
CM CM CM
Link layer overhead
Connection layer overhead
90N