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UC San Diego Computer Engineering
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VLSI CAD Laboratory
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UC San Diego Computer Engineering
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VLSI CAD Laboratory
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UC San Diego Computer Engineering
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VLSI CAD Laboratory
UC San
Tuck-Boon Chan†
Andrew B. Kahng†‡
ECE† & CSE‡ Depts.,
UC San Diego
MOTIVATION
Resist
Hardmask
Metal
1) Overlay
RC VARIATION ANALYSIS
(a)
W1
Color 1
Color 2
SR
25%
Cs
Cc
45nm
VLSI CAD Laboratory
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UC San Diego Computer Engineering
1) Pattern interconnect using DPL reduces capacitance
variation by 20% (from 23% to 17%) compared to
single patterning lithography (SPL)
Redundant stitching reduces variability
2) Capacitance variation of symmetric case is 15%
(from 20% to 17%) less than the asymmetric case
victim
(c)
SL
Cc
X
Cs
2 lines
Y
STITCHING IMPACT ON DELAY
Calculate capacitance at different stitching
locations using 45nm commercial parameters
stitching location
interconnect length
Color 1
driver
midpoint
3 lines DPL asym.
22nm technology
20.00%
15.00%
10.00%
1
Stitching at midpoint minimizes RC variation
No difference between asym. and sym. DPL
at midpoint
7
9 11 13 15 17 19 21
stitching location
2 lines DPL
CONCLUSIONS
45nm technology
20.00%
1) Optimizing stitching location in DPL
reduces 3 delay variation by 25%
(from 20% to 15%)
2) Optimal stitching location is at
midpoint along an interconnect but
slightly shifted toward driver’s side
due to resistance shielding effect
15.00%
10.00%
1
3
5
7
9 11 13 15 17 19 21
stitching location
 Optimal stitching location shifts to the
driver side due to resistance shielding
 Similar trends for 45nm and 22nm
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x1/(x1 +x2) (%)
5
VLSI CAD Laboratory
x1/(x1 +x2) (%)
3
2 lines SPL
25.00%
3/Mean delay (%)
midpoint
2 lines DPL
3/Mean delay (%)
3 lines DPL Asymmetric
3/ capacitance (%)
3 lines DPL symmetric
2 lines SPL
3 lines DPL
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3 lines SPL
receiver
20 RC modules
3 lines SPL
25.00%
Color 2
UC San Diego Computer Engineering
3/ capacitance (%)
Color 2 length : x2
Stitching location
Color 2
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Color 1 length : x1
Color 1
VLSI CAD Laboratory
Assign RC module before stitch location
to Color 1 and after stitching location to
Color 2
Simulate circuit delay using 22nm
(predictive technology) and 45nm
(commercial) HSPICE models
delay
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UC San Diego Computer Engineering
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VLSI CAD Laboratory
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neighbor
STITCHING IMPACT ON RC
VLSI CAD Laboratory
3 lines SPL 3 lines DPL 3 lines DPL 2 lines SPL 2 lines DPL
symmetric asymmetric
UC San Diego Computer Engineering
UC San
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0%
3 lines asymmetric
Ground
plane
5%
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UC San Diego Computer Engineering
Ground
plane
10%
Cs
Cc
1) Interconnect has less RC variation with
uncorrelated RC distribution than with
correlated RC distribution due to
averaging effect
2) Stitching on long/critical interconnect
 uncorrelated RC values
 less timing variability
SR
SL
15%
VLSI CAD Laboratory
(b)
neighbors
20%
VLSI CAD Laboratory
VLSI CAD Laboratory
victim
Capacitance variation
3/ (%)
3 lines symmetric
22nm
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T
H
Ground
plane
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SL
W2
 Study three interconnect patterns
 Derive analytical equations for interconnect RC
 Use 45nm (commercial) and 22nm (ITRS)
parameters to calculate interconnect RC values
neighbors
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DPL prints layout shapes in two exposures
 Uncorrelated CD distribution
 Different-color interconnects have
uncorrelated RC distribution
victim
UC San Diego Computer Engineering
BIMODALITY IN DPL
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Final patterns
Can LELE pattern stitching strategy
reduce on-chip timing variability?
What is the “best-practice” for
choosing stitching location?
Is redundant stitching better?
stitches
Interconnect
spacing variation
2) Independent exposures
Uncorrelated
1st Exp.
2nd Exp.
critical dimension
(CD) variation
VLSI CAD Laboratory
2nd Exp.
2nd Exp.
UC San Diego Computer Engineering
1st Exp.
2nd Etch
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Questions:
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1st Exp.
& Etch
UC San Diego Computer Engineering
Different stitching locations are
possible for double patterning
Patterning variations in LELE double
patterning lithography (DPL)
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UC San Diego Computer Engineering
Performance and Variability Driven Guidelines for BEOL
Layout Decomposition with LELE Double Patterning
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