Chapter 12
Basic Relay Instructions
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Objectives
Describe the function of the normally
open, or examine if closed, instruction.
Describe the function of the normally
closed, or examine if open, instruction.
Explain the function of one-shot
instruction.
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Objectives (cont’d.)
Explain the function and programming of
the latch and unlatch instructions.
Explain input and output instruction
formatting for the SLC 500 and MicroLogix
PLCs.
Given an address, identify the input or
output point on an SLC 500 fixed or
modular PLC and a MicroLogix 1000 PLC.
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PLC Instructions
Each PLC manufacturer has their own
vocabulary of instructions called the
PLC instruction set.
Even though different PLCs have
different instruction sets, there are basic
instructions shared by all PLCs.
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Bit or Relay Instructions
Contacts and coils are the basic
symbols found on a ladder program.
Normally open and normally closed
instructions are programmed to
represent input conditions.
Contacts and coils are referred to as
relay instructions.
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Overview of Bit Instructions
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SLC 500 XIC Instruction
SLC 500 normally open instruction is
called the XIC or examine if closed
instruction.
XIC instruction directs the processor to
test for an on condition from the
referenced address bit.
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XIC Instruction Interaction
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XIC Input Instruction
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SLC 500 XIO Instruction
SLC 500 normally closed instruction is
called the XIO or examine if open
instruction.
XIO instruction directs the processor to
test for an off condition from the
referenced address bit.
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SLC 500 XIO Instruction (cont’d.)
The XIO instruction is normally closed,
representing a 0 in the input status
table.
Finding a 0 in the status file referencing
the instruction address means the
device controlling the bit address is in
the off condition.
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SLC 500 XIO Instruction (cont’d.)
A normally closed instruction evaluated
as closed is a true instruction.
Finding the normally closed instruction
true, the instruction will continue to
provide continuity through the
instruction on the rung.
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Instruction Controlling
an Output Instruction
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Physical Input Conditions and the
Normally Closed XIO Instruction
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SLC 500 Output Instruction
Typically represented as an output coil.
SLC 500 refers to as an output enable
or OTE instruction.
Every rung must have an output
instruction.
Multiple outputs must be programmed
in parallel.
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SLC 500 Output Instruction (cont’d.)
Output instruction is always the last
instruction before the right power rail.
Output instruction represents the action
to be taken when the solved input logic
results in a logically true or false rung.
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Ladder Rung Containing
XIC and OTE Instructions
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Bit Instruction Addressing
Each instruction on a ladder rung must
have an address that associates with
the field device and data table the
instruction is examining.
Typical XIC address is I:1/0.
Typical OTE address is O:2/1.
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Basic SLC 500 Input
or Output Addressing Format
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I:1/0 Breakdown
I = this is an input instruction. Input
address data is stored in the input
status file.
: = element delimiter. Separate file type
and file number.
1 = identifies the chassis slot in which
the addresses module resides.
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I:1/0 Breakdown (cont’d.)
/ = bit delimiter. Separates the input bit
slot reference from the input bit
reference.
1 = screw terminal number of this input
reference from the input module
residing in chassis slot 1.
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Slot Identification in an
SLC 500 Chassis
To accurately identify a specific input
point among multiple input modules,
each slot in a modular chassis is
assigned a slot number.
Power supply mounts on the left side of
the chassis.
First slot next to power supply is
reserved for the processor.
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Slot Identification in an
SLC 500 Chassis (cont’d.)
Processor always goes in the first slot,
which is identified as slot 0.
Slots are numbered in decimal numbers
from left to right: slot 0, 1, 2, 3, 4, 5, 6.
Four chassis available.
4-, 7-, 10-, and 13-slot chassis.
Total 3 chassis 30 local I/O slots per
PLC.
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Seven-Slot SLC 500
Chassis Slot Identification
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The One-Shot Rising Instruction
One-shot rising instruction (OSR) is an
input instruction that allows an event to
occur only once.
OSR instruction fires on the rising edge
(off to on transition) of the input pulse.
Will not fire again until input transitions
to off and then on.
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SLC 500 Family
One-Shot Rising Ladder Rung
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Leading-Edge Versus Trailing-Edge
One-Shot Timing Diagram
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Internal Bit Controlling
a One-Shot Instruction
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Output Latch and
Unlatch Instruction
An output latch (OTL) instruction is an
output instruction used to maintain, or
latch, an output on even if the status of
the input logic changes.
The output unlatch (OUT) instruction is
used to unlatch the latched output.
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Output Latch and
Unlatch Instruction (cont’d.)
OTL and OTU instructions are typically
used in pairs.
OTU is used by itself to unlatch status
bits set by the processor.
OTL and OUT are retentive instructions.
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Retentive Instructions
Two types of instructions:
Non retentive
Retentive
Non retentive instructions do not retain their
logical state through a rung true to false
transition or power interruption.
Retentive instruction retains its logical state
through a rung transition or a power flow
interruption.
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Retentive Instructions (cont’d.)
Retentive must have battery backup to
retain state through power interruption.
OTE instruction is non retentive.
OTL and OUT instructions are retentive.
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Latching and
Unlatching Ladder Logic
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Latching Instruction Programmed
before the Unlatch Instruction
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Internal Bit B3:0/0
Used as an Output
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Each Bit File Element
Consists of One 16-Bit Word
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Bit File Addressing
B = this is a bit instruction. Bit file
address data is stored in the Binary or
bit file, B3.
3 = identifies this as file 3.
: = element delimiter. Separate file type
and file number.
1 = identifies the element number.
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Bit File Addressing (cont’d.)
/ = bit delimiter. Separates the file
designator from the bit number.
1 = bit number of this reference from bit
file element 1.
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User-Defined Bit Files
If your processor supports expanding
data files and has enough memory, any
data file over file 8 up to 255 can be
created as a user-defined bit file.
Each user-defined file can have up to
256 elements.
Sample addresses: B10:4/8 or
B65:29/12.
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