DK1 Power Presentation
2
BC466
1
SC1U10V 5KX
2
1
R51 0
1R3 F
5
SC1476_A GND
R12 3
10R3
U29
PH5330
SC1476_A GND
35
16
H_V ID5
H_V ID4
H_V ID3
H_V ID2
H_V ID1
H_V ID0
1
4 H_V ID[5:0]
2
R15 2
100K R3
3
ISH1
PWRGD
CL1
VID5
VID4
VID3
VID2
VID1
VID0
CMP1
CLRF
CMPRF
CMP2
CLS ET
HY S
CL2
DA C
1
R18 2
24K 9R3F
SC1000P 50V3K X
Proto-1B
1476_ ISH1
33
1476_ CL1
32
1476_ CMP 1
31
1476_ CLRF
29
1476_ CMP RF
28
1476_ CMP 2
27
1476_ CL2
26
1476_ ISH2
24
1476_ DAC
18
19
21
22
1476_ DH2
1476_ LX2
1476_ DL2
S.B.
1
R15 0
1
R48 6
1
R48 5
1
R48 4
1
R48 3
1
R45 7
1
R45 6
1
R45 5
1
R45 4
2
10K R3F
2
825R3F
2
499R3F
2
845R3F
2
432R3F
2
499R3F
2
825R3F
2
10K R3F
2
619R3F
U69
IRF7811A
1
2
Revised : N50D00/Rock Lin
Instructed : N50D10/Jim C Chen
S
S
S
G
SC1U10V 5KX
B05 30W
Presentation Title
PWR_SRC
SC1476_A GND
D49
1
*SD
BC101
SC1000P 50V3K X
R14 9
1R3 F
SC1476_A GND
•
•
*SD
SC1476ITST R
BC463
BS T2_V CORE
SC1476_A GND
*SD
D
D
D
D
C22 4
SCD01U16V2K X
S.B.
BC465
2
VDPR
SS
TG2
DRN2
BG2
PGND2
34
S
5
6
7
8
1476_ VDRP 5
15
25
20 GND
17 V5_2
BST2
R18 4
15K R3F
Proto-1B
PB OOT
1476_ DH1
1476_ LX1
1476_ DL1
1
SC1476_A GND
ISH2
R18 3
16K 5R3F
Proto-1B
1476_ PBOOT 6
1
Vboot=1.2V
Vdpr=0.749V
BC464
SC1000P 50V3K X
7
8
EN
1
2
R15 1
30K 1R3F
2
R18 1
61K 9R3F
2
2
C22 5
SCD1U16V3K X
1
1476_ CLSE T
1476_ HYS
1
VCORE_PWRGD
9
10
11
12
13
14
DP RS L
2
1
37
36
4
3
2
1
34 VCORE_PWRGD
TG1
DRN1
BG1
PGND1
2
16 DP RS LPVR
29,33,34,38 RUNP WROK
VCCA
G
1
2
3
4
4
BST1
30
1476_ VCCA
CORE
V5_1
BC102
SC1U10V 5KX
SC1476_A GND
23
38
D
U67
DK1 Block Diagram
2
Presentation Title
Power on sequence block diagram

3
Please link to >>>>>>
Presentation Title
Procedure Of Checking KBC Pulses
1) Use probe to touch the CN11 pin 2 ( DEBUG_TXD )
without inserting AC adapter.
2) As for oscilloscope, set up Trigger Mode : Normal.
3) Final step that have to insert AC adapter but do
not press Power Button.
4) Eventually, we should have 4 set of pulses as
below.
4
Presentation Title
Good Sign From KBC
5
Presentation Title
Procedure Of Checking KBC Pulses
a) If we couldn't have such pulses from KBC.
b) Please go back to check the signal step by step.
ACAV_IN
MAX1999_SHDN#
3D3V_S5
X1( PIN 1, 2, XTAL )
DEBUG_OUT.
c) There are several circuit portion listed below.
6
Presentation Title
Procedure Of Checking KBC Pulses
7
Presentation Title
Procedure Of Checking KBC Pulses
U55
8
Presentation Title
Procedure Of Checking KBC Pulses
9
Presentation Title
Procedure Of Checking KBC Pulses
10
Presentation Title
Procedure Of Checking No Power Issues
• Symptom : 3 LED light turn on entirely (FPC)
First Case:
a) Firstly, you can jump to check VCC_CORE_S0 power plane.
b) Does CPU power comes up?
c) If doesn't . Please go back to check with the
power sequence from beginning as 5V_S3/+3VSRC
SUSPWROK
1D8V_S3/1D5V_S3
RUN_ON_D
1D05V_S0
VCC_CORE_S0 .
d) These action will check which power plane have no power up.
e) The more detailed power sequence waveform have attached
from page 12 to page 21.
11
Presentation Title
Procedure Of Checking No Power Issues
Second Case:
a) Assumed that CPU voltage can attain 0.9 Volt above.
b) We may prove that the rest of power plane before
VCC_CORE_S0 power plane would be fine.
c) Afterward, please check with ICH_PCIRST#
H_CPURST# .
( See fig.1, fig.2 below )
d) If ICH_PCIRST# still can’t exist, we can check the following
signal : RESET_OUT#( From KBC)
VRM_PWRGD.
e) If H_CPURST# can’t driven high, the following action should
take is checking the GMCH_PWROK( R431 pin 2 ).
f) In addition, we can check whether reference voltage (2/3 VCCP)
for GMCH correct or not, that is, GTLREF, H_VREF.
( R38 pin 1, GTLREF ), ( R311 pin 1, H_VREF ).
12
Presentation Title
Fig.1 ( H_PWRGD, ICH_PCIRST# )
13
Presentation Title
Fig.2 ( H_CPURST#, ICH_PCIRST# )
14
Presentation Title
Procedure Of Checking No Power Issues
1) If both H_PWRGD and H_CPURST# driven high as
fig.1, fig.2. We’ll keep tracking the next signal which
connect between CPU and GMCH, that is, H_ADS#.
( Fig.3 ).
2) We can assume that CPU may failure if we can’t
get these pulses in Fig.3.
3) Another case is only show up one pulse in Fig.3
that we can suspect the failure in U40 ( Bios Rom ).
15
Presentation Title
Fig.3 ( H_ADS# )
H_ADS# is the “first signal” generated by CPU ,
18
16
GTL_ADS#
Presentation Title
CPU to NB
Test pad only .
LPC_LFRAME# WAVEFORM COME OUT AFTER
H_ADS# PRODUCED BY CPU ( REFER TO PAGE 20 )
17
Presentation Title
By the way, If above signal OK. Then we can check the rest of
CLK waveforms.
1) Check U62 ( clock GEN ) RN45, RN46 pin 3, 4
( 100/133 MHz ).
18
Presentation Title
CPU CLK
2) Check memory CLK ( 200/266 MHz ) which asserts from GMCH.
Practically, we can probe the DDR socket ( normal type ) at pin 35,
37.
19
Presentation Title
CPU access BIOS data flow
VCC Clock
VCC Clock
H_ADS#
CPU
DMI_RXP/N
N/B
H_TRDY#
H_CPURST#
H_D#(63:0)
20
VCC Clock
Presentation Title
VCC Clock
LPC_LFRAME#
S/B
DMI_TXP/N
BIOS
LPC_LAD(3:0)
Reset
Reset
DK1 POWER SEQUENCE WAVEFORM
Test Purpose:
Overview of Procedure:
Timing Variable
T01
T02
T03
T04
T05
T06
T06-1
T07
T08
T09
T10
T11
To record the timing sequence for the power rails.
Measure the timing of the power rails. The definition of these timing
variables is given in the power sequencing document attached below this
Time table. Comments
60.00 us Time of AD+ to DCBATOUT
200.00 us Time of AD+ to ACAV_IN
20.00 us Time of DCBATOUT to +3D3VRTC
31.20 us Time of ACAV_IN to MAX1999_SHDN#
2.18 ms Time of MAX1999_SHDN# to 3D3V_S5
176.00 us Time of MAX1999_SHDN# to 5V_S5
32.7ms Time of 3D3V_S5 to EC_RST#
59.20 ms Time of SYS_PWRB# to +3V_SRC
329.00 ms Time of SYS_PWRB# to AUX_EN#
61.20 ms Time of SYS_PWRB# to SUS_ON
380.00 us Time of SUS_ON to 5V_S3
400.00 us Time of SUS_ON to 3VSUS_ON
T12
T13
T14
T15
T16
T17
268.00 ms
2.58 ms
1.40 ms
16.00 us
1.51 ms
2.21 ms
Time of
Time of
Time of
Time of
Time of
Time of
SUS_ON to +15V
SUS_ON to ICH_RSMRST#
3VSUS_ON to 3D3V_S3
5V_S3 to +15V
5V_S3 to SUSPWROK_1999
5V_S3 to ICH_RSMRST#
T18
T19
T20
T21
T22
820.00 us
2.98 ms
1.94 ms
98.00 ms
98.40 ms
Time of
Time of
Time of
Time of
Time of
SUSPWROK_1999 to 1D5V_S3
SUSPWROK_1999 to 1D8V_S3
1D8V_S3 to DDR_VREF_S3
ICH_RSMRST# to ICH_SLP_S3#
ICH_RSMRST# to RUN_ON
T23
T24
T25
T26
T27
T28
106.00 ms
1.08 us
752.00 us
248.00 us
2.02 ms
400 us
Time of
Time of
Time of
Time of
Time of
Time of
ICH_RSMRST# to RUN_PWROK
ICH_SLP_S3# to PM_PWRBTN#
ICH_SLP_S3# to 5V_S0
ICH_SLP_S3# to 1D5V_S0
ICH_SLP_S3# to RUN_ON_D
RUN_ON_D to 3D3V_S0
T29
T30
T31
T32
T33
T34
T35
T36
576.00 us
1.21 ms
6.52 ms
6.14 ms
1.78 ms
140.00 us
Time of
Time of
Time of
Time of
Time of
Time of
Time of
Time of
RUN_ON_D to 2D5V_S0
RUN_ON_D to 1D05V_S0
RUN_ON_D to RUN_PWROK
3D3V_S0 to RUN_PWROK
RUN_PWROK to VCC_CORE_S0
VCC_CORE_S0 to CLK_PWRGD#
VCC_CORE_S0 to VRM_PWRGD
VCC_CORE_S0 to RESET_OUT#
T37
T38
T39
T40
Section Owner:
Section Tester:
Time To Complete:
Date Finished:
4.42 ms Time of
145.00 ms Time of
1.04 ms Time of
992.00 us Time of
Jim C Chen
Abel Chang
06/15
06/15
21
4.54 ms
-7.60 ms
Presentation Title
CLK_PWRGD# to VRM_PWRGD
RESET_OUT# to ICH6_PWROK
ICH6_PWROK to ICH_PCIRST#
ICH_PCIRST# to H_CPURST#