The Imagine Stream
Processor
Ujval J. Kapasi, William J.
Dally, Scott Rixner, John D.
Owens, and Brucek Khailany
Presenter: Lu Hao
Contents
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Stream processor
Imagine Architecture
Example: FFT application
Experimental result
Conclusion
Motivation of stream processor
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Media-processing applications, such as 3-D polygon rendering,
MPEG-2 encoding are becoming an increasingly dominant portion of
computing workloads today
Properties of media-processing applications
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Real-time performance constraints
High arithmetic intensity require parallel solutions
Inherently contain a large amount of data-parallelism
Providing large numbers of ALUs to operate on data in parallel is
relatively inexpensive
Current programmable solutions cannot scale to support this many
ALUs
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Both providing instructions and transferring data at the necessary rates
are problematic.
For example, a 48 ALU single-chip processor must issue up to 48
instructions/cycle and provide up to 144 words/cycle of data bandwidth to
operate at peak rate.
What is a stream processor
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Usually SIMD
Allows some applications to more
easily exploit a limited form of parallel
processing
Using the stream programming
model to expose parallelism as well as
producer-consumer locality
can use multiple computational units
The Imagine Processor
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Imagine is a programmable stream processor and
is a hardware implementation of the stream model.
Imagine is designed to be a stream coprocessor for
a general purpose processor that acts as the host.
The programming model organizes the computation
in an application into a sequence of arithmetic
kernels, and organizes the data-flow into a series of
data streams.
On a variety of realistic applications, Imagine can
sustain up to 50 instructions per cycle, and up to 15
GOPS of arithmetic bandwidth.
Load-store architecture for streams (SRF)
Contents
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Stream processor
Imagine Architecture
Example: FFT application
Experimental result
Conclusion
Architecture of Imagine
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32 KW stream
register file (SRF)
The microcontroller
keeps track of the
program counter as
it broadcasts each
VLIW instruction to
all eight clusters in
a SIMD manner.
Each ALU cluster:
six ALUs and 304
registers in several
local register files
(LRFs).
Architecture of Imagine
The SRF
The SRF
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Clusters <---> SRF: data that needs to
be passed from kernel to kernel
SRF <---> DRAM: part of truly global
data structures
All stream operands originate in the
SRF and stream results are stored
back to the SRF.
Irregular stream locality converted
to reuse through memory
Irregular producer-consumer
locality captured at the SRF
Data distribution
Data distribution result
Architecture of Imagine
The ALU cluster
The ALU cluster
256 x 32-bit
register file
Contents
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Stream processor
Imagine Architecture
Example: FFT application
Experimental result
Conclusion
Example: mapping of a 1024-point
radix-2 FFT to the stream model
Contents
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Stream processor
Imagine Architecture
Example: FFT application
Experimental result
Conclusion
Experimental Result
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Speedup of 8 clusters over 1 cluster
Contents
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Stream processor
Imagine Architecture
Example: FFT application
Experimental result
Conclusion
Conclusion
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Stream processors are suitable for mediaprocessing applications
Imagine exploits the data-level parallelism
(DLP) in streams by executing a kernel on
eight successive stream elements in parallel
(one on each cluster).
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SRF
ALU clusters
Application example: 1024pt FFT
Thanks!
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Questions?