Lecture 22:
PLLs and
DLLs
Outline
 Clock System Architecture
 Phase-Locked Loops
 Delay-Locked Loops
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
2
Clock Generation
 Low frequency:
– Buffer input clock and drive to all registers
 High frequency
– Buffer delay introduces large skew relative to
input clocks
• Makes it difficult to sample input data
– Distributing a very fast clock on a PCB is hard
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
3
Zero-Delay Buffer
 If the periodic clock is delayed by Tc, it is
indistinguishable from the original clock
 Build feedback system to guarantee this delay
Phase-Locked
Loop (PLL)
Delay-Locked
Loop (DLL)
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
4
Frequency Multiplication
 PLLs can multiply the clock frequency
– Distribute a lower frequency on the board
– Multiply it up on-chip
– Possible to adjust the frequency on the fly
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
5
Phase and Frequency
 Analyze PLLs and DLLs in term of phase F(t) rather
than voltage v(t)
1 F  t  mod 2  
clk  
0 F  t  mod 2  
t
F  t   2  f  t dt
0
 Input and output clocks may
deviate from locked phase
– Small signal analysis
22: PLLs and DLLs
F in  t   F  t   F in  t 
F out  t   N F  t   F out  t 
CMOS VLSI Design 4th Ed.
6
Linear System Model
 Treat PLL/DLL as a linear system
– Compute deviation F from locked position
– Assume small deviations from locked
– Treat system as linear for these small changes
 Analysis is not valid far from lock
– e.g. during acquisition at startup
 Continuous time assumption
– PLL/DLL is really a discrete time system
• Updates once per cycle
– If the bandwidth << 1/10 clock freq, treat as continuous
 Use Laplace transforms and standard analysis of linear
continuous-time feedback control systems
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
7
Phase-Locked Loop (PLL)
 System
 Linear Model
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
8
Voltage-Controlled Oscillator
 VCO
Vctrl  t   Vctrl0  Vctrl  t 
f out
 K vco
Vctrl
+-
F out  s  2 K vco

Vctrl  s 
s
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
9
Alternative Delay Elements
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
10
Frequency Divider
 Divide clock by N
– Use mod-N counter
f out
f fb 
N
F out
F fb 
N
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
11
Phase Detector
 Difference of input and
feedback clock phase
 Often built from phase-frequency detector (PFD)
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
12
Phase Detector
 Convert up and down pulses into current proportional to phase
error using a charge pump
I pd  s 
Ferr  s 

22: PLLs and DLLs
I cp
2
 K pd
CMOS VLSI Design 4th Ed.
13
Loop Filter
 Convert charge pump
current into Vctrl
 Use proportional-integral control (PI) to generate a
control signal dependent on the error and its integral
– Drives error to 0
Vctrl  s  1

R
I pd  s  sC
22: PLLs and DLLs
(negligible)
CMOS VLSI Design 4th Ed.
14
PLL Loop Dynamics
 Closed loop transfer function of PLL
1  2 K vco

K pd  R 

F out  s 
sC  s

H s 

1
1  2 K vco
F in  s 

1  K pd  R 

N
sC  s

 This is a second order system
H s  N
2zwn s  w
s 2  2zwn s  wn2
2
n
wn 
z 
I cp K vco
NC
wn
2
RC
 wn indicates loop bandwidth
 z indicates damping; choose 0.7 – 1 to avoid ringing
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
15
Delay Locked Loop
 Delays input clock rather than creating a new clock
with an oscillator
 Cannot perform frequency multiplication
 More stable and easier to design
– 1st order rather than 2nd
 State variable is now time (T)
– Locks when loop delay is exactly Tc
– Deviations of T from locked value
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
16
Delay-Locked Loop (DLL)
 System
 Linear Model
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
17
Delay Line
 Delay input clock
 Typically use voltage-controlled delay line
Tout  s 
 Kvcdl
Vctrl  s 
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
18
Phase Detector
 Detect phase error
 Typically use PFD and charge pump, as in PLL
I pd  s 
Terr  s 

22: PLLs and DLLs
I cp
Tc
CMOS VLSI Design 4th Ed.
19
Loop Filter
 Convert error current
into control voltage
 Integral control is sufficient
 Typically use a capacitor as the loop filter
Vctrl  s  K I
1


I pd  s 
s
sC
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
20
DLL Loop Dynamics
 Closed loop transfer function of DLL
Tout  s 
1
H s 

Tin  s  st  1
 This is a first order system
CTc
1
t

K pd K I Kvcdl I cp Kvcdl
 t indicates time constant (inverse of bandwidth)
– Choose at least 10Tc for continuous time approx.
22: PLLs and DLLs
CMOS VLSI Design 4th Ed.
21